Xilinx Zynq-7000 User Manual page 15

X-Ref Target - Figure 2-1
I/O Peripherals
SPI 0
SPI 1
I2C 0
Bank0
I2C 1
MIO
CAN 0
(15:0)
CAN 1
UART 0
UART 1
GPIO
I/O
SD 0
MUX
SD 1
(MIO) USB 0
USB 1
Enet 0
Enet 1
Bank1
MIO
FLASH Memory
(53:16)
Interfaces
SRAM/NOR
NAND
Quad SPI
Input Clock
Clock
Generation
and Freq
0 1 2 3
Extended
MIO (EMIO) PS to PL
Clock Ports
PS I2C-1
(EMIO)
M M
Local Pcore
EDK IP
Third Party IP
CORE Generator EDK IP
AXI Interface
Video Interface
AXI Streaming
Interface
Video
In
Video Sync Signals
1080p
Monitor
Figure 2-1: Zynq-7000 AP SoC Base TRD Hardware Block Diagram
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Processing System (PS)
Reset
SWDT
TTC
System
Level
Control
Regs
DMA 8
Channel
Central
Interconnect Components
DMA Sync
32b GP 32b GP
0 1 2 3
AXI AXI
Master Slave
Ports Ports
M
S
AXI Interconnect
M M M M M M
HDMI_IN
VID_IN_AXI4S TPG_0
VIDEO_MUX_0
VTC_0
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Application Processor Unit (APU)
NEON/FPU Engine
Cortex-A9
MMU MPCore
CPU
32 KB I 32 KB D
Cache Cache
GIC Snoop Control Unit
512 KB L2 Cache and Controller
255 KB OCM
OCM
Interconnect
CoreSight
DAP
Programmable
DEVC
Logic to Memory
Interconnect
12 13 14 15
8 9 10 11
4 5 6 7
0 1 2 3
High Performance
IRQ
AXI 32b/64b
Slave Ports
Perf
Mon
Master
AXI Interconnect
Slave Slave
S2MM
TPG VDMA
LOGICVC_0
YUV2RGB_0
CRESAMPLE_0
Video
Out
1080p
Hardware Architecture
NEON/FPU Engine
Cortex-A9
MMU MPCore
CPU
32 KB I 32 KB D
Cache Cache
BootROM
Memory Interfaces
DDR2/3, LPDDR2
Controller
Master
AXI Interconnect
Slave Slave
MM2S S2MM
Sobel VDMA
Sobel Filter
UG925_c2_01_020514
Send Feedback
64b
AXI ACP
Slave
Port
15