Pcie Interface - Quectel LTE-A Module Series Hardware Design

NOTE
"*" means under development.

3.8. PCIe Interface

EM120R-GL and EM160R-GL provide one integrated PCIe (Peripheral Component Interconnect Express)
interface which complies with the PCI Express Specification, Revision 2.1 and supports 5 Gbps per lane.
The PCIe interface is used for data transmission, GNSS NMEA sentences output, software debugging
and firmware upgrade.
The following table shows the pin definition of PCIe interface.
Table 12: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
I/O Description
AI/AO PCIe reference clock (+)
AI/AO PCIe reference clock (-)
AI PCIe receive data (+)
AI PCIe receive data (-)
AO PCIe transmit data (+)
AO PCIe transmit data (-)
PCIe reset input.
DI
Active low.
PCIe clock request.
DO
Active low.
PCIe wake up the host.
DO
Active low.
LTE-A Module Series
Comment
Require differential impedance
of 95 Ω.
Require differential impedance
of 95 Ω
Require differential impedance
of 95 Ω
3.3 V power domain
3.3 V power domain
3.3 V power domain
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