U)Sim Interfaces - Quectel LTE-A Module Series Hardware Design

The reset scenario is illustrated in the following figure.
VCC (H)
FULL_CARD_POWER_OFF#
RESET#
PCIE_RST_N
Figure 16: Timing of Resetting the Module
Table 9: Timing of Resetting the Module
Index Min. Typical
T1 0 ms 20 ms
T2 0 ms 10 ms
T3 0 ms 20 ms
T4 - 100 ms
T5 200 ms -
NOTE
Please ensure that there is no large capacitance on RESET# pin.

3.6. (U)SIM Interfaces

The (U)SIM interfaces circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM
cards are supported, and Dual SIM Single Standby* function is supported.
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
T2
T5
T1
Max. Comments
- PCIE_RST_N should be asserted before RESET#.
RESET# should be asserted before
200 ms
FULL_CARD_POWER_OFF#.
RESET# should be de-asserted after
200 ms
FULL_CARD_POWER_OFF#
PCIE_RST_N should be de-asserted 100 ms after
-
FULL_CARD_POWER_OFF#.
RESET# should be de-asserted no longer than 700 ms,
700 ms
otherwise the module would reset several times.
LTE-A Module Series
T3
T4
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