Quectel LTE-A Module Series Hardware Design page 45

PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
The following table shows the pin definition of PCM interface which can be applied on audio codec
design.
Table 14: Pin Definition of PCM Interface
Pin Name Pin No. I/O
PCM_DIN 22 DI
PCM_DOUT 24 DO
PCM_SYNC 28 IO
PCM_CLK 20 IO
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Refer to
document [3] for details about AT+QDAI command.
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
125 μs
1 2
MSB
MSB
Figure 26: Auxiliary Mode Timing
Description
PCM data input
PCM data output
PCM data frame
synchronization
PCM data bit clock
In master mode, it is an
output signal.
In slave mode, it is an input
signal.
LTE-A Module Series
31 32
LSB
LSB
Comment
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain.
If unused, keep it open.
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