Quectel LTE-A Module Series Hardware Design page 28

The turn-on scenario is illustrated in the following figure.
VCC
RESET#
FULL_CARD_POWER_OFF#
DPR/ANT_CONFIG
PCIE_RST_N
Figure 9: Turn-on Timing of the Module
Table 6: Description of Turn-on Timing of the Module
Index Min. Typical
T1 0 ms 50 ms
T2 0 ms 20 ms
T3 0 ms 15 ms
T4 - 100 ms
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
T1
T2
T3
T4
Typical 11.6 s
OFF Booting
Max. Comment
RESET# is pulled up internally, and it would be
-
de-asserted 50 ms after VCC is powered on.
FULL_CARD_POWER_OFF# could be de-asserted
- before or after RESET#, 20 ms is a recommended value
when it is controlled by GPIO.
DPR or ANT_CONFIG should be asserted before
20 ms
modem initialize.
PCIE_RST_N should be de-asserted 100 ms after
-
FULL_CARD_POWER_OFF#.
LTE-A Module Series
Active
27 / 79