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Quectel LTE-A Series Hardware Design

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EG18
Hardware Design
LTE-A Module Series
Rev. EG18_Hardware_Design_V1.1
Date: 2019-12-21
Status: Released
www.quectel.com

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  • Page 1 EG18 Hardware Design LTE-A Module Series Rev. EG18_Hardware_Design_V1.1 Date: 2019-12-21 Status: Released www.quectel.com...
  • Page 2 QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION.

  • Page 3: About The Document

    LTE-A Module Series EG18 Hardware Design About the Document History Revision Date Author Description Oscar LIU/ 2019-07-25 Initial Xavier XIA Updated the current consumption and sensitivity data of EG18-NA; Updated the timing information of powering on, powering off, resetting, (U)SIM and USB in Archibald JIANG/ 2019-12-21 Chapter 3;...

  • Page 4: Table Of Contents

    LTE-A Module Series EG18 Hardware Design Contents About the Document ........................... 2 Contents ............................... 3 Table Index ..............................6 Figure Index ..............................8 Introduction ............................10 1.1. Safety Information........................11 Product Concept ..........................12 2.1. General Description ......................... 12 2.2. Key Features ...........................
  • Page 5 LTE-A Module Series EG18 Hardware Design 3.11. SPI Interface* ........................... 53 3.12. PCM and I2C Interfaces ......................55 3.13. ADC Interfaces ........................57 3.14. Network Status Indication ......................58 3.15. Operation Status Indication ..................... 60 3.16. RI Behaviors ..........................60 3.17.
  • Page 6 LTE-A Module Series EG18 Hardware Design Mechanical Dimensions ........................93 7.1. Mechanical Dimensions of the Module..................93 7.2. Recommended Footprint ......................95 7.3. Design Effect Drawings of the Module ..................96 Storage, Manufacturing and Packaging ..................97 8.1. Storage ............................ 97 8.2.
  • Page 7 LTE-A Module Series EG18 Hardware Design Table Index TABLE 1: FREQUENCY BANDS, CA COMBINATIONS AND GNSS TYPES OF EG18 MODULE....12 TABLE 2: KEY FEATURES OF EG18 ....................... 14 TABLE 3: I/O PARAMETERS DEFINITION ...................... 20 TABLE 4: PIN DESCRIPTION ........................... 20 TABLE 5: OVERVIEW OF OPERATING MODES ....................
  • Page 8 LTE-A Module Series EG18 Hardware Design TABLE 42: EG18-NA CURRENT CONSUMPTION ..................85 TABLE 43: RF OUTPUT POWER ........................87 TABLE 44: EG18-EA CONDUCTED RF RECEIVING SENSITIVITY ............... 87 TABLE 45: EG18-NA CONDUCTED RF RECEIVING SENSITIVITY ............... 88 TABLE 46: ELECTROSTATIC DISCHARGE CHARACTERISTICS ..............89 TABLE 47: RECOMMENDED THERMAL PROFILE PARAMETERS ..............
  • Page 9 LTE-A Module Series EG18 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ....................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) ....................19 FIGURE 3: DRX RUN TIME AND CURRENT CONSUMPTION IN SLEEP MODE ......... 32 FIGURE 4: SLEEP MODE APPLICATION VIA UART INTERFACES .............. 33 FIGURE 5: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP ............
  • Page 10 LTE-A Module Series EG18 Hardware Design FIGURE 40: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) ................................... 77 FIGURE 41: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) ................................... 78 FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ..........79 FIGURE 43: MECHANICALS OF U.FL-LP CONNECTORS ................

  • Page 11: Introduction

    LTE-A Module Series EG18 Hardware Design Introduction This document defines EG18 module and describes its air interface and hardware interfaces which are connected to customers’ applications. This document helps customers quickly understand interface specifications, electrical and mechanical details, as well as other related technical information of EG18 module. Associated with relevant application notes and user guides, the module will be used to design and set up mobile applications easily.

  • Page 12: Safety Information

    EG18 module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for any user’s failure to observe these precautions.

  • Page 13: Product Concept

    LTE-A Module Series EG18 Hardware Design Product Concept 2.1. General Description EG18 is a series LTE-FDD/LTE-TDD/WCDMA wireless communication module with diversity reception. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. EG18 supports embedded operating systems such as Windows, Linux and Android. It also provides GNSS and voice functionality to meet specific application demands.
  • Page 14 LTE-A Module Series EG18 Hardware Design B2+B4+B5*/B13*/B71*; B1+B3+B3/B5/B7/B8/B20/B28/B38/B41; B2+B5+B66; B2+B12+B30; B1+B40+B40; B1+B41+B41; B2+B13+B66; B2+B7+B12/B66; B1+B7+B20; B4+B30+B5/B12/B29; B3+B3+B7/B20/B28; B4+B7+B12; B3+B7+B7/B8/B20/B28; 3×CA (DL) B30+B66+B5/B12/B29; B3+B40+B40; B2+B2+B5/B12/B13/B29/B66; B3+B41+B41; B5+B5+B2/B30/B66; B7+B7+B20/B28; B7+B7+B2/B4/B5; B40+B40+B40; B66+B66+B2/B5/B13/B66; B41+B41+B41 B41+B41+B25/B26/B41; B1+B3+B3+B5/B7/B8/B28/B41; B2+B4+B30+B5/B12; B1+B3+B7+B5/B7/B8/B20/B28; B2+B66+B66+B5/B13; 4×CA (DL) B3+B3+B7+B7/B20/B28; B5+B5+B66+B66; B3+B7+B7+B20/B28;...

  • Page 15: Key Features

    LTE-A Module Series EG18 Hardware Design 2.2. Key Features The following table describes the detailed features of EG18. Table 2: Key Features of EG18 Feature Details Supply voltage: 3.3V~4.3V Power Supply Typical supply voltage: 3.8V Class 3 (23dBm± 2dB) for LTE-TDD bands Transmitting Power Class 3 (23dBm±...
  • Page 16 Rx-diversity Support LTE/WCDMA Rx-diversity and LTE HO-diversity Gen9HT-Lite of Qualcomm GNSS Features Protocol: NMEA 0183 Comply with 3GPP TS 27.007 and 27.005, and Quectel enhanced AT AT Commands commands Two pins (NET_MODE and NET_STATUS) to indicate network connectivity Network Indication...

  • Page 17: Functional Diagram

    LTE-A Module Series EG18 Hardware Design NOTES “*” means under development. Within operating temperature range, the module is 3GPP compliant. Within extended temperature range, proper mounting, heating sinks and active cooling may be required to make certain functions of the module such as voice, SMS, data transmission to be realized.

  • Page 18: Evaluation Board

    EG18 Hardware Design 2.4. Evaluation Board To help with the development of applications with EG18, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, earphone, antenna, and other peripherals to control or test the module. For more details, please refer to document [2].

  • Page 19: Application Interfaces

    LTE-A Module Series EG18 Hardware Design Application Interfaces EG18 is designed with 299 LGA pins that can be connected to cellular application platform. This chapter mainly describes the following application interfaces and indication signals of EG18:  Power supply  (U)SIM interfaces ...

  • Page 20: Pin Assignment

    LTE-A Module Series EG18 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of EG18. VBAT_RF VBAT_RF VBAT_RF VBAT_RF RESERVED VDD_P2 DBG_RXD DBG_TXD USIM2_CLK GPIO_1 GPIO_2 USIM2_RST USB_BOOT USIM2_DET USIM2_DATA OTG_PWR_EN USIM2_VDD SLEEP_IND RFFE_DATA COEX_UART_TX COEX_UART_RX RESERVED RFFE_CLK NET_MODE WLAN_EN...

  • Page 21: Pin Description

    LTE-A Module Series EG18 Hardware Design NOTES Keep all RESERVED pins and unused pins unconnected. The GND pins 215~299 should be connected to ground in the design. 3.2. Pin Description Table 3: I/O Parameters Definition Type Description Analog Input Analog Output Digital Input Digital Output Bidirectional...
  • Page 22 LTE-A Module Series EG18 Hardware Design If an SD card is used, connect VDD_P2 to SD card power SD_VDD. VDD_P2 supply If an eMMC* is used or SDIO interface is unused, connect VDD_P2 to VDD_EXT. Provide 1.8V for Vnorm=1.8V VDD_EXT external circuit.
  • Page 23 LTE-A Module Series EG18 Hardware Design Status Indication Pin Name Pin No. Description DC Characteristics Comment Indicate the 1.8V power domain. min=1.35V module’s network NET_MODE If unused, keep it max=0.45V registration mode. open. Indicate the 1.8V power domain. min=1.35V module’s network NET_STATUS If unused, keep it max=0.45V...
  • Page 24 LTE-A Module Series EG18 Hardware Design (U)SIM1 card max=0.36V min=1.26V max=0.4V min=1.45V For 3.0V (U)SIM: max=0.57V min=2.0V max=0.4V min=2.3V For 1.8V (U)SIM: Either 1.8V or 3.0V Vmax=1.9V is supported by the Vmin=1.7V module Power supply for USIM2_VDD automatically. (U)SIM2 card For 3.0V (U)SIM: If (U)SIM2 interface Vmax=3.05V...
  • Page 25 LTE-A Module Series EG18 Hardware Design For 3.0V (U)SIM: max=0.4V min=2.3V USB Interface Pin Name Pin No. Description DC Characteristics Comment Vmax=5.25V USB connection USB_VBUS Vmin=3.3V detection Vnorm=5.0V USB 2.0 differential Comply with USB USB_DM data bus (-) 2.0 standard specifications.
  • Page 26 LTE-A Module Series EG18 Hardware Design min=-0.3V open. max=0.58V SDIO data signal (bit If unused, keep it min=1.3V SD_DATA2 open. max=2.0V SDIO data signal (bit If unused, keep it SD_DATA3 open. For 3.0V SD card: SDIO command If unused, keep it max=0.35V SD_CMD signal...
  • Page 27 LTE-A Module Series EG18 Hardware Design will wake up the module. If unused, keep it open. Debug UART Interface Pin Name Pin No. Description DC Characteristics Comment min=-0.3V 1.8V power domain. max=0.6V DBG_RXD Receive data If unused, keep it min=1.2V open.
  • Page 28 LTE-A Module Series EG18 Hardware Design min=1.2V open. max=2.0V BT UART interface pin by default. Can be multiplexed into SPI_CS. PCM & I2C Interfaces Pin Name Pin No. Description DC Characteristics Comment 1.8V power domain. I2C_SDA I2C serial interface An external pull-up used for external resistor is required.
  • Page 29 LTE-A Module Series EG18 Hardware Design Support all band 4x4 them open. ANT_ MIMO1 MIMO antenna interface Support all band 4x4 ANT_MIMO2 MIMO antenna interface GNSS antenna ANT_GNSS interface WLAN Control Interface* Pin Name Pin No. Description DC Characteristics Comment 1.8V power domain.
  • Page 30 LTE-A Module Series EG18 Hardware Design PCIe Interface* Pin Name Pin No. Description DC Characteristics Comment Input/Output PCIe PCIE_REFCLK_P 179 reference clock (+) PCIE_REFCLK_ Input/Output PCIe Comply with PCIe reference clock (-) 2.1 standard PCIE_TX_M PCIe transmission (-) specifications. Require differential PCIE_TX_P PCIe transmission (+) impedance of 95Ω.
  • Page 31 LTE-A Module Series EG18 Hardware Design Antenna Tuner Control Interfaces* (RFFE Interface/GPIO Interface) Pin Name Pin Name Description DC Characteristics Comment max=0.45V RFFE_CLK min=1.35V RFFE serial max=0.45V If unused, keep interface used for min=1.35V them open. external tuner min=-0.3V RFFE_DATA control max=0.6V min=1.2V...

  • Page 32: Operating Modes

    LTE-A Module Series EG18 Hardware Design RESERVED Pins Pin Name Pin No. Description DC Characteristics Comment 4, 6~9, 11, 12, 14, 15, 18~23, 72, 91, 95, Keep these pins Reserved RESERVED 134, 176, unconnected. 192~195, 197~201, 209~213 3.3. Operating Modes The table below summarizes different operating modes of EG18.

  • Page 33: Power Saving

    LTE-A Module Series EG18 Hardware Design 3.4. Power Saving 3.4.1. Sleep Mode DRX of EG18 is able to reduce the current consumption to a minimum value during the sleep mode, and DRX cycle index values are broadcasted by the wireless network. The figure below shows the relationship between the DRX run time and the current consumption in sleep mode.

  • Page 34: Usb Application With Usb Remote Wakeup Function

    LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Figure 4: Sleep Mode Application via UART Interfaces  Driving the host DTR to low level will wake up the module.  When EG18 has a URC to report, RI signal will wake up the host.

  • Page 35: Usb Application With Usb Suspend/Resume And Ri Function

    LTE-A Module Series EG18 Hardware Design  Sending data to EG18 through USB will wake up the module.  When EG18 has a URC to report, the module will send remote wake-up signals via USB bus to wake up the host. 3.4.1.3.

  • Page 36: Airplane Mode

    LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Module Host GPIO Power USB_VBUS Switch USB Interface USB Interface EINT Figure 7: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match of the connection shown in dotted line between the module and the host.

  • Page 37: Power Supply

    LTE-A Module Series EG18 Hardware Design AT+CFUN=0 Low Level AT+CFUN=1 RF Disabled Airplane mode AT+CFUN=4 NOTES The W_DISABLE# control function is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol" command, and this command is under development. 2. The execution of AT+CFUN command will not affect GNSS function. 3.5.

  • Page 38: Decrease Voltage Drop

    LTE-A Module Series EG18 Hardware Design 3.5.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V. Please make sure the input voltage will never drop below 3.3V. The following figure shows the maximum voltage drop when burst transmission occurs during radio transmission in 3G and 4G networks.

  • Page 39: Reference Design For Power Supply

    LTE-A Module Series EG18 Hardware Design 3.5.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply of EG18 should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, an LDO is suggested to be used to supply power for the module.

  • Page 40: Turn On And Off Scenarios

    LTE-A Module Series EG18 Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Turn on the Module Through PWRKEY The following table shows the pin definition of PWRKEY. Table 8: PWRKEY Pin Description Pin Name Pin No. Description DC Characteristics Comment max=2.1V 1.8V power domain.
  • Page 41 LTE-A Module Series EG18 Hardware Design Another way to control the PWRKEY is using a button. Electrostatic strike may generate from fingers when the button is pressed. Therefore, it is necessary to place a TVS component nearby the button for ESD protection.

  • Page 42: Turn Off The Module

    LTE-A Module Series EG18 Hardware Design 3.6.2. Turn off the Module The following two methods can be used to turn off the module: through PWRKEY or AT+QPOWD command. 3.6.2.1. Turn off the Module Through PWRKEY Driving PWRKEY to a low level voltage for at least 800ms, then the module will execute power-down procedure after the PWRKEY is released.

  • Page 43: Reset The Module

    LTE-A Module Series EG18 Hardware Design NOTES To avoid damages to the internal flash, please do not switch off the power supply directly when the module is working. Only after the module is shut down by PWRKEY or AT command can the power supply be cut off.
  • Page 44 LTE-A Module Series EG18 Hardware Design RESET_N Close to S2 Figure 16: Reference Circuit of RESET_N with a Button The timing of reset scenario is illustrated by the following figure. VBAT ≤600ms ≥1.3V RESET_N ≤0.5V ≥212.5ms ≥2.5ms VDD_EXT ≥204ms ≥17s VDD_RF ≥205ms ≥16s...

  • Page 45: U)Sim Interfaces

    LTE-A Module Series EG18 Hardware Design 3.8. (U)SIM Interfaces EG18 provides two (U)SIM interfaces. The circuitry of (U)SIM interfaces meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported. Dual SIM Single Standby function is supported and (U)SIM card switching is enabled by AT+QUIMSLOT command. For more details about this command, please refer to document [3].
  • Page 46 LTE-A Module Series EG18 Hardware Design The following figure shows a reference design for a (U)SIM interface with an 8-pin (U)SIM card connector. VDD_EXT USIM_VDD 100nF (U)SIM Card Connector USIM_VDD USIM_RST Module USIM_CLK USIM_DET USIM_DATA NM NM Figure 18: Reference Circuit of a (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET pins unconnected.
  • Page 47 LTE-A Module Series EG18 Hardware Design The (U)SIM scenario is illustrated by the following figure. ≥5.8ms USIM_VDD ≥1.1ms USIM_DATA ≥1.7ms USIM_CLK USIM_CLK ≥20.8ms USIM_RST Figure 20: Timing of (U)SIM When AT+QSIMDET=1,0 is set, the scenario of hot-plug is illustrated by the following figure. USIM_DET ≥103ms ≥5.8ms...

  • Page 48: Usb Interface

    LTE-A Module Series EG18 Hardware Design  Keep (U)SIM card signals away from RF and VBAT traces.  Keep the ground traces between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. ...
  • Page 49 LTE-A Module Series EG18 Hardware Design For more details about the USB 2.0 and USB 3.0 specifications, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in design. The following figure shows a reference circuit of USB 2.0 and USB 3.0 interface. Test Points Minimize these stubs Host...
  • Page 50 LTE-A Module Series EG18 Hardware Design The USB enumeration scenario is illustrated by the following figure. Figure 23: Timing of USB Enumeration The following principles of USB interface should be complied with, so as to meet USB 2.0 and USB 3.0 specifications.

  • Page 51: Uart Interfaces

    LTE-A Module Series EG18 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: main UART interface, debug UART interface, and BT UART interface. Features of these interfaces are shown as below:  Main UART interface supports 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps (default), 230400bps, 460800bps, and 921600bps baud rates.

  • Page 52: Debug Uart Interface

    LTE-A Module Series EG18 Hardware Design 3.10.2. Debug UART Interface The following table shows the pin definition of debug UART interface. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. Description Comment DBG_RXD Receive data 1.8V power domain DBG_TXD Transmit data 1.8V power domain...
  • Page 53 LTE-A Module Series EG18 Hardware Design 0.45 1.35 A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design. VDD_EXT VCCA VCCB VDD_MCU 0.1μF 0.1μF VDD_EXT 120K RI_MCU DCD_MCU Translator CTS_MCU RTS_MCU DTR_MCU RXD_MCU TXD_MCU Figure 24: Level Translation Reference Circuit with an IC Please visit http://www.ti.com for more information.

  • Page 54: Spi Interface

    LTE-A Module Series EG18 Hardware Design Another example with transistor translation circuit is shown as below. The circuit designs for the parts shown with dotted lines refer to the design of TXD and RXD, and please pay attention to the direction of connection.
  • Page 55 LTE-A Module Series EG18 Hardware Design BT_RXD Can be multiplexed into SPI_MISO. BT_RTS Can be multiplexed into SPI_CS. The following figure shows the timing of SPI Interface. Figure 26: Timing of SPI Interface The related parameters of SPI timing are listed in the following table. Table 17: Parameters of SPI Interface Timing Parameter Description...

  • Page 56: Pcm And I2C Interfaces

    LTE-A Module Series EG18 Hardware Design 3.12. PCM and I2C Interfaces EG18 supports audio communication via Pulse Code Modulation (PCM) digital interface and I2C interfaces. The PCM interface supports the following modes:  Primary mode (short frame synchronization, works as both master and slave) ...
  • Page 57 LTE-A Module Series EG18 Hardware Design 125μs PCM_CLK PCM_SYNC PCM_OUT PCM_IN Figure 28: Auxiliary Mode Timing The following table shows the pin definition of PCM interface and I2C interface, both of which can be applied on audio codec design. Table 18: Pin Definition of PCM interface and I2C Interface Pin Name Pin No.

  • Page 58: Adc Interfaces

    LTE-A Module Series EG18 Hardware Design Clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to document [3] for details about AT+QDAI command. The following figure shows a reference design of PCM interface with an external codec IC.

  • Page 59: Network Status Indication

    LTE-A Module Series EG18 Hardware Design In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground. Table 19: Pin Definition of the ADC Interfaces Pin Name Pin No. Description General purpose analog to digital converter interface. ADC0 If unused, keep it open.
  • Page 60 LTE-A Module Series EG18 Hardware Design Indicate the module’s network 1.8V power domain NET_STATUS activity status. If unused, keep it open. Table 22: Working State of the Network Status/Activity Indicator Pin Name Status Description Always High Registered on network NET_MODE Always Low Others Flicker slowly (200ms High/1800ms Low)

  • Page 61: Operation Status Indication

    LTE-A Module Series EG18 Hardware Design 3.15. Operation Status Indication The STATUS pin is set as the module status indicator. It outputs high level voltage when the module is turned on. The following table describes pin definition of STATUS pin. Table 23: Pin Definition of STATUS Pin Name Pin No.

  • Page 62: Pcie Interface

    LTE-A Module Series EG18 Hardware Design In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below. Table 24: RI Behaviors State Response Idle RI keeps at high level RI outputs 120ms low pulse when a new URC returns The RI behavior can be changed by executing AT+QCFG="urc/ri/ring"...
  • Page 63 LTE-A Module Series EG18 Hardware Design In master mode, it is an input signal. PCIE_CLK_REQ_N PCIe clock request In slave mode, it is an output signal. If unused, keep it open. In master mode, it is an output signal. PCIE_RST_N PCIe reset In slave mode, it is an input signal.

  • Page 64: Root Complex Mode

    LTE-A Module Series EG18 Hardware Design 3.17.1. Root Complex Mode In this mode, the module is configured to act as a PCIe RC device. The following figure shows a reference circuit of PCIe RC mode. Module WLAN 100nF PCIE_RX_P PCIE_TX_P 100nF PCIE_RX_M PCIE_TX_M...

  • Page 65: Endpoint Mode

    LTE-A Module Series EG18 Hardware Design 3.17.2. Endpoint Mode In this mode, the module is configured to act as a PCIe EP device. The following figure shows a reference circuit of PCIe EP mode. Test Points Minimize these stubs NM_0R NM_0R Module Host...

  • Page 66: Sdio Interface

    LTE-A Module Series EG18 Hardware Design matching should be less than 2mm (15ps).  For PCIe signal traces, the maximum length of each differential data pair (TX/RX) is recommended to be less than 250mm, and each differential data pair matching should be less than 0.7mm (5ps). ...
  • Page 67 LTE-A Module Series EG18 Hardware Design The following figure shows an SDIO interface reference design. Module SD Card Connector VDD_EXT VDD_2V85 SD_VDD 100μF 100nF 33pF 10pF 100K 100K 100K 100K 100K 470K R1 0R SD_DATA3 CD/DAT3 R2 0R SD_DATA2 DAT2 R3 0R SD_DATA1 DAT1...

  • Page 68: Antenna Tuner Control Interfaces

    LTE-A Module Series EG18 Hardware Design 3.19. Antenna Tuner Control Interfaces* The module provides two methods to control external antenna tuner: through RFFE signals or GPIO signals. Customers can choose either one according to their tuner design. The following table lists the pin definitions of these RFFE and GPIO signals.

  • Page 69: Usb_Boot Interface

    LTE-A Module Series EG18 Hardware Design GPIO_5 If unused, keep it open. VDD_RF Provide 2.85V for external RF circuit. If unused, keep it open. NOTE “*” means under development. 3.20. USB_BOOT Interface EG18 provides a USB_BOOT pin. Developers can pull up USB_BOOT to VDD_EXT before powering on the module, to make the module enter into emergency download mode when powered on.

  • Page 70: Gpios

    LTE-A Module Series EG18 Hardware Design 3.21. GPIOs In addition to the three GPIOs dedicated for external tuner control, the module provides 2 GPIOs for customers’ design. Table 30: Pin Definition of GPIOs Pin Name Pin No. Description Comment GPIO_1 If unused, keep it open.

  • Page 71: Gnss Receiver

    LTE-A Module Series EG18 Hardware Design GNSS Receiver 4.1. General Description EG18 includes a fully integrated global navigation satellite system solution that supports Gen9HT-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EG18 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default.

  • Page 72: Layout Guidelines

    LTE-A Module Series EG18 Hardware Design Autonomous Hot start @open sky XTRA enabled Accuracy Autonomous CEP-50 (GNSS) @open sky 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers’ design.  Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna. ...

  • Page 73: Antenna Interfaces

    LTE-A Module Series EG18 Hardware Design Antenna Interfaces EG18 provides a main antenna interface, an Rx-diversity antenna interface, two MIMO antenna interfaces, and a GNSS antenna interface. The impedance of antenna ports is 50Ω. 5.1. Main/Rx-diversity/MIMO Antenna Interfaces 5.1.1. Pin Definition The pin definition of main antenna interface, Rx-diversity antenna interface and MIMO antenna interfaces is shown as below.
  • Page 74 LTE-A Module Series EG18 Hardware Design LTE B1 1920~1979.9 2110~2169.9 LTE B3 1710~1784.9 1805~1879.9 LTE B5 824~848.9 869~893.9 LTE B7 2500~2569.9 2620~2689.9 LTE B8 880~914.9 925~959.9 LTE B20 832~861.9 791~820.9 LTE B28 703~747.9 758~802.9 LTE B38 2570~2619.9 2570~2619.9 LTE B40 2300~2399.9 2300~2399.9 LTE B41...

  • Page 75: Reference Design Of Rf Antenna Interfaces

    LTE-A Module Series EG18 Hardware Design LTE B30 2305~2315 2350~2360 LTE B41 2496~2689.9 2496~2689.9 LTE B66 1710~1780 2110~2200 LTE B71 617~652 663~698 5.1.3. Reference Design of RF Antenna Interfaces A reference design of ANT_MAIN, ANT_DIV, ANT_MIMO1 and ANT_MIMO2 interfaces is shown as below.

  • Page 76: Gnss Antenna Interface

    LTE-A Module Series EG18 Hardware Design 5.2. GNSS Antenna Interface 5.2.1. Pin Definition The following tables show pin definition and frequency specification of GNSS antenna interface. Table 35: Pin Definition of GNSS Antenna Interface Pin Name Pin No. Description Comment ANT_GNSS GNSS antenna interface 50Ω...

  • Page 77: Reference Design Of Gnss Antenna Interface

    LTE-A Module Series EG18 Hardware Design 5.2.3. Reference Design of GNSS Antenna Interface A reference design of GNSS antenna is shown as below. Figure 37: Reference Circuit of GNSS Antenna Interface NOTES An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed.

  • Page 78: Reference Design Of Rf Layout

    LTE-A Module Series EG18 Hardware Design 5.3. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds...

  • Page 79: Antenna Installation

    LTE-A Module Series EG18 Hardware Design Figure 41: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:  Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω.

  • Page 80: Recommended Rf Connector For Antenna Installation

    LTE-A Module Series EG18 Hardware Design Active antenna gain: >0dBi Active antenna embedded LNA gain: <17dB VSWR: ≤ 2 Efficiency: >30% Max Input Power: 50W Input Impedance: 50Ω Cable Insertion Loss: <1dB (WCDMA B5/B8/, WCDMA/LTE LTE B5/B8/B12/B13/B14/B20/B26/B28/B29/B71) Cable Insertion Loss: <1.5dB (WCDMA B1/B2/B3/B4/, LTE B1/B2/B3/B4/B25/B66) Cable Insertion Loss <2dB...
  • Page 81 LTE-A Module Series EG18 Hardware Design U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT. Figure 43: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mating plugs. Figure 44: Space Factor of Mating Plugs (Unit: mm) For more details, please visit http://www.hirose.com.

  • Page 82: Electrical, Reliability And Radio Characteristics

    LTE-A Module Series EG18 Hardware Design Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 38: Absolute Maximum Ratings Parameter Min.

  • Page 83: Power Supply Ratings

    LTE-A Module Series EG18 Hardware Design 6.2. Power Supply Ratings Table 39: The Module’s Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit The actual input voltages must stay VBAT_BB and VBAT between the minimum and VBAT_RF maximum values. USB connection USB_VBUS 5.25...

  • Page 84: Current Consumption

    LTE-A Module Series EG18 Hardware Design 6.4. Current Consumption 6.4.1. EG18-EA Current Consumption Table 41: EG18-EA Current Consumption Parameter Description Conditions Typ. Unit μA OFF state Power down VBAT AT+CFUN=0 (USB disconnected) 0.98 WCDMA PF=64 (USB disconnected) 2.51 WCDMA PF=128 (USB disconnected) 1.94 WCDMA PF=256 (USB disconnected) 1.62...
  • Page 85 LTE-A Module Series EG18 Hardware Design LTE-TDD PF=64 (USB active) 24.97 WCDMA B1 HSDPA CH10700 @23.4dBm WCDMA B1 HSUPA CH10700 @23.5dBm WCDMA B3 HSDPA CH1338 @23.3dBm WCDMA data WCDMA B3 HSUPA CH1338 @23.4dBm transfer (GNSS VBAT WCDMA B5 HSDPA CH4407 @23.4dBm OFF) WCDMA B5 HSUPA CH4407 @23.3dBm WCDMA B8 HSDPA CH3012 @23.3dBm...

  • Page 86: Eg18-Na Current Consumption

    LTE-A Module Series EG18 Hardware Design 6.4.2. EG18-NA Current Consumption Table 42: EG18-NA Current Consumption Parameter Description Conditions Typ. Unit μA OFF state Power down VBAT AT+CFUN=0 (USB disconnected) 1.08 WCDMA PF=64 (USB disconnected) 2.53 WCDMA PF=128 (USB disconnected) 2.05 WCDMA PF=256 (USB disconnected) 1.81 WCDMA PF=512 (USB disconnected)
  • Page 87 LTE-A Module Series EG18 Hardware Design WCDMA B2 HSDPA CH9800 @22.89dBm 678.24 WCDMA B2 HSUPA CH9800 @22.94dBm 669.07 WCDMA B4 HSDPA CH1412 @23.22dBm 543.58 WCDMA data transfer VBAT (GNSS OFF) WCDMA B4 HSUPA CH1412 @23.2dBm 579.04 WCDMA B5 HSDPA CH4407 @23.4dBm 553.84 WCDMA B5 HSUPA CH4407 @23.3dBm 558.13...

  • Page 88: Rf Output Power

    LTE-A Module Series EG18 Hardware Design 6.5. RF Output Power The following table shows the RF output power of EG18. Table 43: RF Output Power Frequency Max. Min. WCDMA bands 24dBm+1/-3dB <-50dBm LTE FDD bands 23dBm± 2dB <-40dBm LTE TDD bands 23dBm±...

  • Page 89: Eg18-Na Receiving Sensitivity

    LTE-A Module Series EG18 Hardware Design LTE-FDD B20 (10M) -98.7dBm -98.8dBm -102.2dBm -93.3dBm LTE-FDD B28 (10M) -99.7dBm -99.7dBm -102.7dBm -94.8dBm LTE-TDD B38 (10M) -98.2dBm -98.5dBm -100.7dBm -96.3dBm LTE-TDD B40 (10M) -98.2dBm -98.9dBm -100.7dBm -96.3dBm LTE-TDD B41 (10M) -97.2dBm -97.4dBm -99.7dBm -94.3dBm 6.6.2.

  • Page 90: Electrostatic Discharge

    LTE-A Module Series EG18 Hardware Design NOTES SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which can improve Rx performance. 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is important to refer ESD handling precautions applying ESD sensitive components.
  • Page 91 LTE-A Module Series EG18 Hardware Design  The heatsink should be designed with as many fins as possible to increase heat dissipation area. Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and module/PCB. The following figures manifest two kinds of heatsink designs for reference. Please choose one or both of them according to particular application structure.
  • Page 92 LTE-A Module Series EG18 Hardware Design In order to protect the components from damage, the thermal design should be optimized to guarantee that the module’s internal temperature maintains below 105°C constantly. AT+QTEMP command can be used to obtain the module’s internal temperature. As shown in the figure below. Figure 47: Response of AT+QTEMP EG18_Hardware_Design 91 / 104...
  • Page 93 LTE-A Module Series EG18 Hardware Design The following figure shows the corresponding position of the eight temperature sensors of the EG18. Figure 48: Temperature Sensor Distribution NOTES Make sure that the PCB design provides sufficient cooling solutions for the module: proper mounting, heatsinks, and active cooling may be required depending on the integrated application.

  • Page 94: Mechanical Dimensions

    LTE-A Module Series EG18 Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and dimensional tolerances are ± 0.05mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Pin1 Figure 49: Module Top and Side Dimensions (Unit: mm) EG18_Hardware_Design 93 / 104...
  • Page 95 LTE-A Module Series EG18 Hardware Design Figure 50: Module Bottom Dimensions (Top View, Unit: mm) EG18_Hardware_Design 94 / 104...

  • Page 96: Recommended Footprint

    LTE-A Module Series EG18 Hardware Design 7.2. Recommended Footprint Figure 51: Recommended Footprint (Top View, Unit: mm) NOTE For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. EG18_Hardware_Design 95 / 104...

  • Page 97: Design Effect Drawings Of The Module

    7.3. Top and Bottom Views of the Module Figure 52: Top View of the Module Figure 53: Bottom View of the Module NOTE These are rendering images of EG18. For authentic appearance, please refer to the module received from Quectel. EG18_Hardware_Design 96 / 104...

  • Page 98: Storage, Manufacturing And Packaging

    LTE-A Module Series EG18 Hardware Design Storage, Manufacturing and Packaging 8.1. Storage EG18 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40º C/90%RH. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: ...

  • Page 99: Manufacturing And Soldering

    LTE-A Module Series EG18 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass.

  • Page 100: Packaging

    LTE-A Module Series EG18 Hardware Design Reflow Zone Max slope 2 to 3° C/sec Reflow time (D: over 220° C) 40 to 60 sec Max temperature 238° C ~ 245° C Cooling down slope 1 to 4° C/sec Reflow Cycle Max reflow cycle 8.3.
  • Page 101 LTE-A Module Series EG18 Hardware Design Figure 56: Reel Specifications (Unit: mm) EG18_Hardware_Design 100 / 104...

  • Page 102: Appendix A References

    LTE-A Module Series EG18 Hardware Design Appendix A References Table 48: Related Documents Document Name Remark Quectel_EG18_CA_Feature EG18 CA features. EVB R2.0 user guide of UMTS and LTE Quectel_UMTS&LTE_EVB_R2.0_User_Guide modules. AT commands manual for EM12, EG12 Quectel_EM12&EG12&EG18_AT_Commands_Manual and EG18 modules. GNSS application note for EM12, EG12 Quectel_EM12&EG12&EG18_GNSS_Application_Note and EG18 modules.
  • Page 103 LTE-A Module Series EG18 Hardware Design Coding Scheme Circuit Switched Data Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air Downlink Discontinuous Reception Data Terminal Ready Discontinuous Transmission Enhanced Full Rate Electrostatic Discharge Equivalent Series Resistance Full Rate GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global...
  • Page 104 LTE-A Module Series EG18 Hardware Design Mobile Originated MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor Mobile Station Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying Radio Frequency RHCP Right Hand Circularly Polarized Receive SGMII Serial Gigabit Media Independent Interface...
  • Page 105 LTE-A Module Series EG18 Hardware Design Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value...
  • Page 106 Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application.
  • Page 107 LTE-A Module Series EG18 Hardware Design re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module.
  • Page 108 LTE-A Module Series EG18 Hardware Design This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna.
  • Page 109 LTE-A Module Series EG18 Hardware Design Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device.
  • Page 110 LTE-A Module Series EG18 Hardware Design 2) Le module é metteur peut ne pas être coï mplanté avec un autre é metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplé mentaires sur l'é metteur ne seront pas nécessaires.
  • Page 111 LTE-A Module Series EG18 Hardware Design L'intégrateur OEM doit être conscient de ne pas fournir des informations à l'utilisateur final quant à la faç on d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intègre ce module.

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Eg18 seriesEg18-eaEg18-na

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