Usb Version And Pcie Only Version - Quectel LTE-A Module Series Hardware Design

Table 13: Description of PCIe Power-on Timing Requirements of the Module
Index Min. Typical
T1 0 ms 20 ms
T2 - 50 ms
T3 - 70 ms
T4 - 100 ms
100 μs
T5 -
The following principles of PCIe interface design should be complied with so as to meet PCIe V2.1
specifications.
⚫
It is important to route the PCIe signal traces as differential pairs with total grounding.
⚫
For PCIe signal traces, the TX and RX differential data pair maximum length is recommended to be
less than 250 mm, the TX and RX differential data pair matching are less than 0.7 mm (5 ps).
⚫
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is
important to route the PCIe differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.

3.8.2. USB Version and PCIe Only Version

Beginning with ES2 (engineering samples), EM120R-GL&EM160R-GL support USB version and PCIe
only version described as below:
USB version:
⚫
Support all USB 3.0/2.0 features
⚫
Support MBIM/QMI/QRTR/AT
⚫
Support firmware upgrade
PCIe only version:
⚫
Support MBIM/QMI/QRTR/AT
⚫
Support BIOS PCIe early initial
⚫
Support firmware upgrade
If EM120R-GL&EM160R-GL work at PCIe only version by burnt eFuse, the modules cannot switch back
to USB version.
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
Max. Comment
FULL_CARD_POWER_OFF# could be de-asserted
- before or after RESET#, 20 ms is a recommended value
when it is controlled by GPIO.
RESET# is pulled up internally, and it would be
-
de-asserted 50 ms after VCC is powered on.
PCIE_CLKREQ_N would be asserted 70 ms after
-
FULL_CARD_POWER_OFF#.
PCIE_RST_N should be de-asserted after
-
PCIE_CLKREQ_N.
The host must ensure that the reference clock is in the
- active clock state for at least a period specified by
T , prior to PCIE_RST_N de-assertion.
PCIE_RST_N-CLK
LTE-A Module Series
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