Quectel LTE-A Module Series Hardware Design page 32

Host
Reset pulse
GPIO
Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit
S1
TVS
Note: The capacitor C1 is recommended to be less than 47 pF.
Figure 15: Reference Circuit of RESET_N with Button
EM120R-GL&EM160R-GL_Hardware_Design
EM120R-GL&EM160R-GL Hardware Design
RESET_N
Q2
NMOS
R4
R5
10Ω
–
200 700 ms
100K
Module
VDD 1.8 V
RESET_N
67
C1
33 pF
–
200 700 ms
LTE-A Module Series
Module
VDD 1.8 V
R1
100K
67
Reset
Logic
R1
100K
Reset
Logic
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