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6.2.5 Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to "1", a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the
nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Clock
Binary counter
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
WDT reset output
17
2
/fc
1
3
0
2
Write 4E
to WDTCR2
H
Figure 6-2 Watchdog Timer Interrupt/Reset
Page 63
RESET
19
2
/fc [s]
1
2
3
(High-Z)
TMP86PM29BUG
pin outputs a low-level sig-
(WDTT=11)
0
A reset occurs
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