Toshiba TLCS-870/C Series Manual page 104

Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the
Note 3: j = 3, 4
Setting port
LD (TTREG4), 3DH
LD (TC4CR), 00010001B
LD (TC4CR), 00011001B
pin to the high level when the TimerCounter is stopped
PDOj
pin to the high level.
PDOj
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÷ ÷
7
: 1/1024 2 /fc 2 = 3DH
7
: Sets the operating clock to fc/2 , and 8-bit PDO mode.
: Starts TC4.
pin holds the output status when the timer is
PDOj
TMP86PM29BUG