Toshiba TLCS-870/C Series Manual page 53

3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
Interrupt Latches
ILH,ILL
(003DH, 003CH)
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers
EIRH,EIRL
(003BH, 003AH)
Note 1: *: Don't care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
15 14 13 12 11
IL15 IL14 IL13 IL12 IL11
ILH (003DH)
IL15 to IL2 Interrupt latches
15 14 13 12 11
EF15 EF14 EF13 EF12 EF11
EIRH (003BH)
Individual-interrupt enable flag
EF15 to EF4
(Specified for each bit)
IMF Interrupt master enable flag
10 9 8 7
IL10 IL9 IL8 IL7 IL6
at RD
0: No interrupt request
1: Interrupt request
10 9 8 7
EF10 EF9 EF8 EF7 EF6
0: Disables the acceptance of each maskable interrupt.
1: Enables the acceptance of each maskable interrupt.
0: Disables the acceptance of all maskable interrupts
1: Enables the acceptance of all maskable interrupts
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TMP86PM29BUG
(Initial value: 00000000 000000**)
6 5 4 3 2
IL5 IL4 IL3 IL2
ILL (003CH)
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
(Initial value: 00000000 0000***0)
6 5 4 3 2
EF5 EF4
EIRL (003AH)
1 0
R/W
1 0
IMF
R/W