Reset Circuit; External Reset Input - Toshiba TLCS-870/C Series Manual

2.3 Reset Circuit

The TMP86PM29BUG has four types of reset generation procedures: An external reset input, an address trap
reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and
the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during
the maximum 24/fc[s] (The
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on.
RESET
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Program counter
Stack pointer
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
Jump status flag
Zero flag
Carry flag
Half carry flag
Sign flag
Overflow flag
Interrupt master enable flag
Interrupt individual enable flags
Interrupt latches

2.3.1 External Reset Input

The pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
RESET
When the
RESET
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-
ized.
When the
RESET
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
pin outputs "L" level).
RESET
pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz).
Initial Value
(PC) (FFFEH)
(SP) Not initialized
Prescaler and divider of timing generator
Not initialized
(JF) Not initialized Watchdog timer
(ZF) Not initialized
(CF) Not initialized
(HF) Not initialized
Output latches of I/O ports
(SF) Not initialized
(VF) Not initialized
(IMF) 0
(EF) 0
Control registers
(IL) 0
LCD data buffer
RAM
pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
pin input goes high, the reset operation is released and the program execution starts at the
Internal reset
Malfunction
reset output
circuit
Figure 2-15 Reset Circuit
Page 31
On-chip Hardware
Refer to I/O port circuitry
Refer to each of control
register
Not initialized
Not initialized
Watchdog timer reset
Address trap reset
System clock reset
TMP86PM29BUG
Initial Value
0
Enable