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TC1 status register
7
TC1SR
HECF
HEOVF
(0016H)
HECF
Operating Status monitor
HEOVF
Counter overflow monitor
8.3 Function
TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode
to NORMAL2 mode.
8.3.1 Timer mode
In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with
the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared.
Counting up resumes after the counter is cleared.
Table 8-1 Source clock (internal clock) of Timer/Counter 1
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0
DV7CK = 1
23
15
fc/2
[Hz]
fs/2
13
fc/2
fs/2
11
fc/2
fs/2
7
fc/2
fc/2
3
fc/2
fc/2
fc
fc
fs
fs
Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper
bits 7 makes interrupts.
6
5
4
"0"
"0"
0:
Stop (during Tb) or disable
1:
Under counting (during Ta)
0:
No overflow
1:
Overflow status
Source Clock
SLOW Mode
SLEEP Mode
15
15
[Hz]
fs/2
[Hz]
fs/2
[Hz]
5
5
5
fs/2
fs/2
3
3
3
fs/2
fs/2
7
-
-
3
-
-
fc (Note)
-
-
-
Page 75
3
2
1
"0"
"0"
"0"
Resolution
fs =32.768
fc = 16 MHz
kHz
0.52 s
1 s
512 ms
0.98 ms
128 ms
244 ms
8 ms
-
0.5 ms
-
62.5 ns
-
-
30.5 ms
TMP86PM29BUG
0
"0"
(Initial value: 0000 0000)
Read
only
Maximum Time Setting
fs =32.768
fc = 16 MHz
kHz
38.2 h
72.8 h
2.2 min
4.3 min
0.6 min
1.07 min
2.1 s
-
131.1 ms
-
16.4 ms
-
-
8 s
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