16-Bit Pulse Width Modulation (Pwm) Output Mode (Tc5 And 6) - Toshiba TLCS-870/C Series Manual

10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)

This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock.
When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the
logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC6 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maxi-
mum frequency to be supplied is fc/2
or SLEEP1/2 mode.
Since the initial value can be set to the timer F/F6 by TC6CR<TFF6>, positive and negative pulses can be
generated. Upon reset, the timer F/F6 is cleared to 0.
(The logic level output from the
Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to
PWREG6 and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG6 and 5. While the timer is
stopped, the values are shifted immediately after the programming of PWREG6 and 5. Set the lower byte
(PWREG5) and upper byte (PWREG6) in this order to program PWREG6 and 5. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG6 and 5 during PWM output, the values set in the shift register is
read, but not the values set in PWREG6 and 5. Therefore, after writing to the PWREG6 and 5, reading data of
PWREG6 and 5 is previous value until INTTC6 is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt
request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC6 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not program
TC6CR<TFF6> upon stopping of the timer.
Example: Fixing the
CLR (TC6CR).3: Stops the timer.
CLR (TC6CR).7 : Sets the
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with-
out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the
pin during the warm-up period time after exiting the STOP mode.
Table 10-7 16-Bit PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
DV7CK = 0 DV7CK = 1
11 3
fc/2 fs/2 [Hz]
7 7
fc/2 fc/2
5 5
fc/2 fc/2
3 3
fc/2 fc/2
fs fs
fc/2 fc/2
fc fc
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
6 pin is the opposite to the timer F/F6 logic level.)
PWM
PWM
6 pin to the high level when the TimerCounter is stopped
PWM
6 pin to the high level.
PWM
Resolution
SLOW1/2,
SLEEP1/2 fc = 16 MHz
mode
128 µs
3
fs/2 [Hz]
8 µs
–
2 µs
–
– 500 ns
30.5 µs
fs
– 125 ns
– 62.5 ns
Page 113
6 pin holds the output status when the timer is
Repeated Cycle
fs = 32.768 kHz fc = 16 MHz
244.14 µs
8.39 s
– 524.3 ms
– 131.1 ms
– 32.8 ms
30.5 µs
2 s
– 8.2 ms
– 4.1 ms
TMP86PM29BUG
4
to in the SLOW1/2
6
PWM
fs = 32.768 kHz
16 s
–
–
–
2 s
–
–