Toshiba TLCS-870/C Series Manual page 17

1.1 Features
7. 8-bit timer counter : 4 ch
8. 8-bit UART/SIO : 1 ch
9. 10-bit successive approximation type AD converter
10. Key-on wakeup : 4 ch
11. LCD driver/controller
12. Clock operation
13. Low power consumption operation
stop.)
oscillate.)
quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
puts(CPU restarts).
ruputs. (CPU restarts).
quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
put.(CPU restarts).
interruput.
14. Wide operation voltage:
- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
Programmable pulse generation (PPG) modes
- Analog input: 8 ch
Built-in voltage booster for LCD driver With display memory
LCD direct drive capability (MAX 32 seg × 4 com)
1/4,1/3,1/2duties or static drive are programmably selectable
Single clock mode
Dual clock mode
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
1.8 V to 5.5 V at 4.2MHz /32.768 kHz
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TMP86PM29BUG
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