Address Trap; Selection Of Address Trap In Internal Ram (Atas); Selection Of Operation At Address Trap (Atout); Address Trap Interrupt (Intatrap) - Toshiba TLCS-870/C Series Manual

6. Watchdog Timer (WDT)

6.3 Address Trap

6.3 Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
Watchdog Timer Control Register 1
7
WDTCR1
(0034H)
ATAS
ATOUT
Watchdog Timer Control Register 2
WDTCR2
(0035H)
WDTCR2

6.3.1 Selection of Address Trap in Internal RAM (ATAS)

WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to "0". To enable the WDTCR1<ATAS> set-
ting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.

6.3.2 Selection of Operation at Address Trap (ATOUT)

When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.

6.3.3 Address Trap Interrupt (INTATRAP)

While WDTCR1<ATOUT> is "0", if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is "1"), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas-
ter flag (IMF).
When an address trap interrupt is generated while the other interrupt including an address trap interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
6 5 4
ATAS ATOUT
Select address trap generation in
the internal RAM area
Select operation at address trap
7 6 5 4
Write
Watchdog timer control code
and address trap area control
code
3 2 1
(WDTEN) (WDTT)
0: Generate no address trap
1: Generate address traps (After setting ATAS to "1", writing the control code
D2H to WDTCR2 is required)
0: Interrupt request
1: Reset request
3 2 1
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
Page 64
TMP86PM29BUG
0
(WDTOUT) (Initial value: **11 1001)
0
(Initial value: **** ****)
Write
only
Write
only