Divider Output (Dvo); Configuration; Control - Toshiba TLCS-870/C Series Manual

7.2 Divider Output (
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from

7.2.1 Configuration

Output latch
D
Data output
MPX
13 5 A
fc/2 or fs/2
B
12 4
fc/2 or fs/2
C
11 3
fc/2 or fs/2
D
10 2
fc/2 or fs/2
S
2
DVOCK
Divider output control register
(a) configuration

7.2.2 Control

The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register
7
TBTCR
DVOEN
(0036H)
DVOEN
DVOCK
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
)
DVO
pin.
DVO
Q
DVO pin
Y
DVOEN
TBTCR
Figure 7-3 Divider Output
6 5 4
DVOCK (DV7CK) (TBTEN)
Divider output
enable / disable
Divider Output ( )
DVO
frequency selection: [Hz]
Page 69
Port output latch
TBTCR<DVOEN>
DVO pin output
(b) Timing chart
3 2 1 0
(TBTCK)
0: Disable
1: Enable
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0 DV7CK = 1
13
00
fc/2
12
01
fc/2
11
10
fc/2
10
11
fc/2
TMP86PM29BUG
(Initial value: 0000 0000)
SLOW1/2
SLEEP1/2
Mode
5 5
fs/2 fs/2
4 4
fs/2 fs/2
3 3
fs/2 fs/2
2 2
fs/2 fs/2
R/W
R/W