Watchdog Timer Disable; Watchdog Timer Interrupt (Intwdt) - Toshiba TLCS-870/C Series Manual

6. Watchdog Timer (WDT)
6.2 Watchdog Timer Control

6.2.3 Watchdog Timer Disable

To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg-
ister in other procedures causes a malfunction of the microcontroller.
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)

6.2.4 Watchdog Timer Interrupt (INTWDT)

When WDTCR1<WDTOUT> is cleared to "0", a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
1. Set the interrupt master flag (IMF) to "0".
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to "0".
4. Set WDTCR2 to the disable code (B1H).
DI
LD (WDTCR2), 04EH
LDW (WDTCR1), 0B101H
WDTT
DV7CK = 0
00 2.097
01 524.288 m
10 131.072 m
11 32.768 m
LD SP, 063FH
LD (WDTCR1), 00001000B
←
: IMF 0
: Clears the binary counter
←
: WDTEN 0, WDTCR2
Watchdog Timer Detection Time[s]
NORMAL1/2 mode
DV7CK = 1
4
1
250 m
62.5 m
: Sets the stack pointer
←
: WDTOUT 0
Page 62
TMP86PM29BUG
←
Disable code
SLOW
mode
4
1
250 m
62.5 m