Table of Contents
Advertisement
15. LCD Driver
15.2 Control
15.2 Control
The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver's display is enabled using
the EDSP.
LCD Driver Control Register
LCDCR
(0028H)
EDSP
EDSP
BRES
VFSEL
DUTY
Note 1: When <BRES>(Booster circuit control) is set to "0", V
When <BRES> is set to "1", 5.5 [V] ≥ V3 ≥ V
If these conditions are not satisfied, it not only affects the quality of LCD display but also may damage the device due to
over voltage of the port.
Note 2: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set LCDCR<DUTY> to "10" or "11"
when the booster circuit is enable.
Note 3: Do not set SLF to "10" or "11" in SLOW1/2 modes.
Note 4: Do not set VFSEL to "11" SLOW1/2 modes.
7
6
5
4
BRES
VFSEL
LCD Display Control
Booster circuit control
Selection of boost frequency
Selection of driving methods
Selection of LCD frame fre-
SLF
quency
3
2
1
DUTY
SLF
0: Blanking
1: Enables LCD display (Blanking is released)
0: Disable (use divider resistance)
1: Enable
NORMAL1/2, IDLE/1/2 mode
DV7CK = 0
DV7CK = 1
13
00
fc/2
fs/2
11
01
fc/2
fs/2
10
10
fc/2
fs/2
9
11
fc/2
fc/2
00: 1/4 Duty (1/3 Bias)
01: 1/3 Duty (1/3 Bias)
10: 1/2 Duty (1/2 Bias)
11: Static
NORMAL1/2, IDLE/1/2 mode
DV7CK = 0
DV7CK = 1
17
00
fc/2
fs/2
16
01
fs/28
fc/2
15
10
fc/2
fc/2
13
11
fc/2
fc/2
≥ V3 ≥ V2 ≥ V1 ≥ V
DD
should be satisfied.
DD
Page 154
TMP86PM29BUG
0
(Initial value: 0000 0000)
SLOW1/2,
SLEEP0/1/2 mode
5
5
fs/2
3
3
fs/2
2
2
fs/2
9
–
SLOW1/2,
SLEEP0/1/2 mode
9
9
fs/2
8
fs/2
15
–
13
–
should be satisfied.
SS
R/W
Advertisement
Table of Contents
