8-Bit Event Counter Mode (Tc6); 8-Bit Programmable Divider Output (Pdo) Mode (Tc6) - Toshiba TLCS-870/C Series Manual

TC6CR<TC6S>
Internal
Source Clock
Counter
TTREG6
?
INTTC6 interrupt request
Figure 10-2 8-Bit Timer Mode Timing Chart (TC6)

10.3.2 8-Bit Event Counter Mode (TC6)

In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/2
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 6
TC6CR<TC6S>
TC6 pin input
Counter 0
TTREG6
?
INTTC6 interrupt request
Figure 10-3 8-Bit Event Counter Mode Timing Chart (TC6)

10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC6)

This mode is used to generate a pulse with a 50% duty cycle from the
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
1 2 3 n-1
n
Match detect
1 2 n-1
n
Match detect
PDOj
Page 107
n 0 1 2 n-1
Counter clear
Match detect
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
PDOj, PWMj
n 0 1 2 n-1 n
Counter
Match detect
clear
PDOj
pin is switched to the opposite state and
PDOj
pin. An arbitrary value can be set to the timer F/Fj by
TMP86PM29BUG
n 0 1 2 0
Counter clear
and pins may output
PPGj
0 1 2 0
Counter
clear
pin.
4