CLR (TC4CR).3: Stops the timer.
CLR (TC4CR).7 : Sets the
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with-
out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the
pin during the warm-up period time after exiting the STOP mode.
Table 9-7 16-Bit PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
DV7CK = 1
11
fc/2
fs/2
7
fc/2
fc/2
5
fc/2
fc/2
3
fc/2
fc/2
fs
fc/2
fc/2
fc
Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)
4 pin to the high level.
PWM
SLOW1/2,
SLEEP1/2
mode
3
3
[Hz]
fs/2
[Hz]
7
–
5
–
3
–
fs
fs
–
fc
–
Setting ports
LDW
(PWREG3), 07D0H
LD
(TC3CR), 33H
LD
(TC4CR), 056H
LD
(TC4CR), 05EH
Resolution
fc = 16 MHz
fs = 32.768 kHz
128 µs
244.14 µs
8 µs
–
2 µs
–
500 ns
–
30.5 µs
30.5 µs
125 ns
–
62.5 ns
–
: Sets the pulse width.
: Sets the operating clock to fc/2
mode (lower byte).
: Sets TFF4 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
: Starts the timer.
Page 95
TMP86PM29BUG
4
PWM
Repeated Cycle
fc = 16 MHz
fs = 32.768 kHz
8.39 s
16 s
524.3 ms
–
131.1 ms
–
32.8 ms
–
2 s
2 s
8.2 ms
–
4.1 ms
–
3
, and 16-bit PWM output