Table Of Contents - Toshiba TLCS-870/C Series Manual

Table of Contents

TMP86PM29BUG
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Operational Description
2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Memory Address Map............................................................................................................................... 9
2.1.2 Program Memory (OTP) ........................................................................................................................... 9
2.1.3 Data Memory (RAM) ................................................................................................................................. 9
2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Clock Generator...................................................................................................................................... 10
2.2.2 Timing Generator .................................................................................................................................... 12
2.2.2.1
Configuration of timing generator
2.2.2.2
Machine cycle
2.2.3 Operation Mode Control Circuit .............................................................................................................. 13
2.2.3.1
Single-clock mode
2.2.3.2
Dual-clock mode
2.2.3.3
STOP mode
2.2.4 Operating Mode Control ......................................................................................................................... 18
2.2.4.1
STOP mode
2.2.4.2
IDLE1/2 mode and SLEEP1/2 mode
2.2.4.3
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
2.2.4.4
SLOW mode
2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1 External Reset Input ............................................................................................................................... 31
2.3.2 Address trap reset .................................................................................................................................. 32
2.3.3 Watchdog timer reset.............................................................................................................................. 32
2.3.4 System clock reset.................................................................................................................................. 32
3. Interrupt Control Circuit
3.1 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 36
3.2.2 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 36
3.3 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.1 Interrupt acceptance processing is packaged as follows........................................................................ 39
3.4.2 Saving/restoring general-purpose registers ............................................................................................ 40
3.4.2.1
Using PUSH and POP instructions
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