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Watchdog Timer Control Register 1
7
6
WDTCR1
(0034H)
WDTEN
Watchdog timer enable/disable
Watchdog timer detection time
WDTT
[s]
WDTOUT
Watchdog timer output select
Note 1: After clearing WDTOUT to "0", the program cannot set it to "1".
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don't care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "6.2.3 Watchdog Timer Disable".
Watchdog Timer Control Register 2
7
6
WDTCR2
(0035H)
Write
WDTCR2
Watchdog timer control code
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don't care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
6.2.2 Watchdog Timer Enable
Setting WDTCR1<WDTEN> to "1" enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to "1" during reset, the watchdog timer is enabled automatically after the reset release.
5
4
3
(ATAS)
(ATOUT)
WDTEN
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
DV7CK = 0
00
01
10
11
0: Interrupt request
1: Reset request
5
4
3
2
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Page 61
2
1
0
WDTT
WDTOUT
NORMAL1/2 mode
DV7CK = 1
25
17
2
/fc
2
/fs
23
15
2
/fc
2
/fs
21
13
2
fc
2
/fs
19
11
2
/fc
2
/fs
1
0
(Initial value: **** ****)
TMP86PM29BUG
(Initial value: **11 1001)
Write
only
SLOW1/2
mode
17
2
/fs
Write
15
only
2
fs
13
2
fs
11
2
/fs
Write
only
Write
only
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