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8. 18-Bit Timer/Counter (TC1)
8.3 Function
8.3.4 Frequency Measurement mode
In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The edge of the ECIN input pulse is counted during "H" level of the window gate pulse selected by
TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to "00".
An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate
pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of
TREG1A while the count is stopped (window gate pulse is low), then clear the counter using
TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.
The window pulse status can be monitored by TC1SR<HECF>.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,
TC1SR<HEOVF> is set to "1". TC1SR<HEOVF> remains the previous data until the counter is required to be
cleared by TC1CR1<TC1C>.
Using TC6 output (
P33
PDO6
(TC1CR2<
operate/stop
When the internal window gate pulse is selected, the window gate pulse is set as follows.
Table 8-2 Internal window gate pulse setting time
Ta
Tb
The internal window gate pulse consists of "H" level period (Ta) that is counting time and "L" level period
(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.
Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be
Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When
Note 3: In case of TC1CR2<SEG> = "1", if window gate pulse becomes falling edge, the up counter stops plus "1"
Note 4: In case of TC1CR2<SEG> = "0", because the up counter is counted on the falling edge of logical AND-ed
/
PWM6
PDO6
can be controlled using TC1CR2<
P33
/
to
; setting 1 in TC1CR2<
PPG6
TC6OUT
> is used to control output to
/
/
.)
PWM6
PDO6
PPG6
Setting "H" level period of the window
gate pulse
Setting "L" level period of the window
gate pulse
delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer.
Tb is overwritten during the Tb period, the update is valid from the next Tb period.
regardless of ECIN input level. Therefore, if ECIN is always "H" or "L" level, count value becomes "1".
pulse (between ECIN pin input and window gate pulse), if window gate pulse becomes falling edge while
ECIN input is "H" level, the up counter stops plus "1". Therefore, if ECIN input is always "H" level, count
value becomes "1".
/
) for the window gate pulse, external output of
PPG6
TC6OUT
>. Zero-clearing TC1CR2<
TC6OUT
> does not output
P33
only. Thus, use the timer counter 6 control register to
NORMAL1/2,IDLE1/2 modes
WGPSCK
DV7CK=0
(16 - Ta) × 2
12
/fc
00
(16 - Ta) × 2
13
01
/fc
10
(16 - Ta) × 2
14
/fc
(16 - Tb) × 2
12
/fc
00
(16 - Tb) × 2
13
01
/fc
10
(16 - Tb) × 2
14
/fc
Page 78
TMP86PM29BUG
PWM6
TC6OUT
/
PWM6
PDO6
SLOW1/2,
SLEEP1/2 modes
DV7CK=1
(16 - Ta) × 2
4
(16 - Ta) × 2
4
/fs
/fs
(16 - Ta) × 2
5
(16 - Ta) × 2
5
/fs
/fs
(16 - Ta) × 2
6
(16 - Ta) × 2
6
/fs
/fs
(16 - Tb) × 2
(16 - Tb) × 2
4
4
/fs
/fs
(16 - Tb) × 2
5
(16 - Tb) × 2
5
/fs
/fs
(16 - Tb) × 2
6
(16 - Tb) × 2
6
/fs
/fs
/
/
to
PDO6
PPG6
> outputs
/
PWM6
P33
/
to
.
PPG6
R/W
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