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8. 18-Bit Timer/Counter (TC1)
8.2 Control
8.2 Control
The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register
(TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B).
Timer register
TREG1AH
(0012H)
R/W
TREG1AM
(0011H)
R/W
TREG1AL
(0010H)
R/W
TREG1B
(0013H)
Ta
Tb
7
6
5
−
−
−
7
6
5
7
6
5
7
6
5
Ta
Setting "H" level period of the window
gate pulse
Setting "L" level period of the window
gate pulse
4
3
2
1
−
−
−
TREG1AH
4
3
2
1
TREG1AM
4
3
2
1
TREG1AL
4
3
2
1
Tb
NORMAL1/2,IDLE1/2 modes
WGPSCK
DV7CK=0
(16 - Ta) × 2
12
/fc
00
(16 - Ta) × 2
13
01
/fc
10
(16 - Ta) × 2
14
/fc
(16 - Tb) × 2
12
/fc
00
(16 - Tb) × 2
13
01
/fc
10
(16 - Tb) × 2
14
/fc
Page 72
TMP86PM29BUG
0
(Initial value: ∗∗∗∗ ∗∗00)
0
(Initial value: 0000 0000)
0
(Initial value: 0000 0000)
0
(Initial value: 0000 0000)
SLOW1/2,
SLEEP1/2 modes
DV7CK=1
(16 - Ta) × 2
4
(16 - Ta) × 2
4
/fs
/fs
(16 - Ta) × 2
5
(16 - Ta) × 2
5
/fs
/fs
(16 - Ta) × 2
(16 - Ta) × 2
6
6
/fs
/fs
(16 - Tb) × 2
(16 - Tb) × 2
4
4
/fs
/fs
(16 - Tb) × 2
5
(16 - Tb) × 2
5
/fs
/fs
(16 - Tb) × 2
6
(16 - Tb) × 2
6
/fs
/fs
R/W
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