Fpga Configuration; 5V Supply Power Monitoring - Xilinx Arty A7 Reference Manual

22.8.2018

3.3 5V Supply Power Monitoring

The Arty A7 includes circuitry for monitoring the voltage of the 5 Volt supply as well as the current consumed from this supply. A
voltage divider is used to scale the 5V input voltage to be within the range (0-1V) that the on-chip 12-bit ADC () is capable of measuring.
The 5V supply voltage is divided by 5.99 and then fed into Auxiliary Channel 1 on the XADC of the Artix-7 FPGA. A combination of a
5 milliohm current sense resistor and a current sense amplifier (IC15, Texas Instruments INA199A1) are used to produce an output
voltage of 250 millivolts per amp of current.This current sense circuit is capable of measuring current between 0 and 2 Amps. Currents
above 4 Amps will not damage the circuit or the FPGA, but will be reported as only 4 Amps. The output of the current sense amplifier is
fed into Auxiliary Channel 9 on the XADC of the Artix-7 FPGA. Applications that wish to monitor the instantaneous power
consumption of the Arty A7 may configure Channels 1 and 9 of the XADC as unipolar inputs and then perform a simultaneous
conversion of the two channels to receive digital values that can be used to compute the instantaneous power consumption. Figure 3.3.1
provides an overview of the circuitry that allows the 5V supply power consumption to be monitored.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-a7/arty-a7-vu-mon.png?id=reference%3Aprogrammable-logic%3Aarty-
a7%3Areference-manual)
Figure 3.3.1 5V Supply Power Monitoring

4 FPGA Configuration

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the
FPGA in one of four ways:
1. A PC can use the Digilent USB-JTAG circuitry (port J10) to program the FPGA any time the power is on.
2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
(https://reference.digilentinc.com/_detail/arty/arty_cfg.png?id=reference%3Aprogrammable-logic%3Aarty-a7%3Areference-manual)
Figure 4.1 Arty A7 Configuration
Figure 4.1 shows the different options available for configuring the FPGA. An on-board "mode" jumper (JP1) selects whether the FPGA
will be programmed by the Quad-SPI flash on power up.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx
can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™
embedded processor-based designs).
Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA's logic functions and circuit connections,
and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a
new configuration file using the JTAG port.
An Artix-7 35T bitstream is typically 17,536,096 bits. The time it takes to program the Arty A7 can be decreased by compressing the
bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on
design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or
Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
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