Extracting The Project Files - Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual

When shipped, the KCU1250 board is configured to support the GTH IBERT demonstrations
described in this document. If the board has been re-configured, it must be returned to the
default setup before running the IBERT demonstrations by following these steps:
1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in the KCU1250 Board User Guide (UG1057)
2. Confirm that the UltraScale transceiver power module is plugged into connectors J124
and J46.
3. Confirm that the SuperClock-2 module
Module User Guide (UG770)
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the KCU1250 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the KCU1250 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50Ω SMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16 and J17.

Extracting the Project Files

The Vivado Design Suite BIT files required to run the IBERT demonstrations are located in
rdf0352-kcu1250-ibert-2017-4.zip on the SD card provided with the KCU1250
board. The BIT files are also available online at
Characterization Kit
The ZIP file contains these BIT files:
• kcu1250_ibert_q224_125.bit
•
kcu1250_ibert_q225_125.bit
• kcu1250_ibert_q226_125.bit
•
kcu1250_ibert_q227_125.bit
•
kcu1250_ibert_q228_125.bit
To copy the files from the SD card:
1. Connect the SD card to the host computer.
2. Locate the file rdf0352-kcu1250-ibert-2017-4.zip on the SD card.
3. Unzip the files to a working directory on the host computer.
KCU1250 IBERT Getting Started Guide
UG1061 (v2017.4) December 20, 2017
is installed. See
[Ref 2]:
documentation.
www.xilinx.com
Chapter 1: KCU1250 IBERT Getting Started Guide
[Ref
HW-CLK-101-SCLK2 SuperClock-2
Kintex UltraScale FPGA KCU1250
1].
6
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