Output Register; Bus Error Logic; Backup Time (For Buffered Sram); Internal Connector - HP M2350A Service Manual

Understanding the Computer Module
The Function Cards
Output
Register
8 bit for status LEDs, test signals and software reset signal
Bus Error
Logic
Minimum 2ms to maximum 4ms delay time out bus-error
Backup Time (for bufFered SRAMJ
Minimum of 3 hours
Internal Connector
96-way ABC
Power Consllmption
4.5 Watts typical
LOCAL
BUS 4
MPB 4
I
DAUGHTER BOARD INTERFACE
I
4
TEMP
SENSOR
,I
-
8
I
/
SERVICE
PORT
68EC030 32
8
' 8
/
/
s
BOOT FLASH SRAM
/
/
Ei '
/-
ROM
ROM 3
s
HOUR
16
1
LED'!
SRAM
I FLASH
/ 0
ROM
DRAM SRAM 3
0
HOUR 8
0
/ MPB
/ INTERFACE
0
Figure 2-6. CPC Block Diagram
2.13