HP M2350A Service Manual page 73

Understanding
Data Transfer
There are buffers on the processor bus to connect to the local bus of the
data to be passed between the processor and the local memory cards.
Memory Array
The memory array for the Utility CPU consists of:
Non-buffered Static RAM (capacity 128 kilobytes).
the Computer Module
The Function Cards
cluster. This allows
EPROM (capacity 64 kilobytes), that contains firmware that is executed when the system is
switched on.
EEPROM (capacity 32 kilobytes), that contains the current configuration of the HP
Component Central Monitor.
Each memory location, on either the CPU card or local memory cards, can be addressed
absolutely using the processor's 23-bit address bus.
Hardware Functions
The following paragraphs describe the basic function of the major components of the Utility
CPU Card with the exception of the MPB Interface Chip. The MPB Interface Chip is described
in the Master Cards section at the beginning of this chapter.
There is a support chip to encode interrupts so the processor can react to interrupts. For
example, power fail (PFAIL) and external interrupt (EXINT) from the local bus.
Address Decoding
The address decoding logic is used, to generate strobes, select signals for the on-board devices
(MPB, SRAM, EPROM). Access acknowledge signals are also generated for all the devices except
the MPB Interface Chip which runs synchronously to the CPU. The MPB Interface generates its
own acknowledge signal.
Bus Error Logic
The bus error logic consists of a timer that watches the microprocessor's address strobe. When
the processor outputs an address on its bus, it asserts the address strobe that a valid memory
address is available. However, if the signal is asserted for too long then the logic assumes
that the access was not terminated correctly, that is, the address strobe was not negated or
removed. The logic then asserts a Bus-Error to tell the processor that it could access the
memory correctly.
PFAIL and SYS-RESET
The PFAIL signal is used to inform all other function cards that a SYS-RESET should be
expected from the UTIL-CPU. One bit of the CPU output latch is used to place PFAIL on the
utility bus.
The PFAIL signal is asserted for two reasons by the CPU:
1. The CPU detects that a serious error has occurred in the system.
2. The watchdog circuit on the MPB-chip detects a failure in the Application CPU.
The PFAIL can also be asserted by the DC/DC Converter when the power is about to fail.
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