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Functional Description
The Keysight E1459A can be programmed to monitor channel occurrences either
internally with a 1.0 MHz sample clock, or externally, with a sourced capture
clock. Using either clocking technique, data channels may function as edge
detect inputs and/or data capture inputs.
Events at any channel may occur simultaneously or in overlap with events on any
other channel. Figure 2 is a block diagram of the hardware interrupt resolver
circuit. User software algorithms are also necessary to resolve issues of overlap
and to determine the occurring sequence of events.
Figure 1-2 Resolver Block Diagram
Watchdog Timer
The Keysight E1459A provides a programmable timer facility which, in the event
of time-out, will generate a "system wide" reset to all other card-cage modules.
This timer may be disabled by the SCPI command DIAG:SYSR:ENAB OFF.
Input Level Selection
Each channel is capable of operation over an input range from 2.0 through 60.0
Vdc. Input voltages are grouped into voltage ranges which are selected via a
series of jumpers on the module. These jumpers are described in more detail
later.
Input Isolation
Each channel is optically coupled and electrically isolated from all other
channels and current paths. Isolated channel inputs are polarized and require
that the user observe input signal polarity when connections are made.
Keysight E1459A/Z2404B User and SCPI Programming Guide
Installing and Configuring the E1459A
13
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