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Register Definitions
Negative Edge Detect Register Port 0/2
The Negative Edge Detect Register for Port 0/2 (base + 16
register captures any high to low transitions with a "1" in this register for any
channel that has been enabled. A channel is enabled by setting a corresponding
bit in the Negative Mask Register. Once the register is read, the data is
automatically cleared. A transition is only seen if it is held long enough to pass
through the debouncers. If bit 4 of the Control/Status Register is low ("0"), Port 0
data is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Negative Edge Detect Register Port 0/2 (Channels 0-15/32-47) (base + 16h)
b +
15
14
13
16
h
Write
No Effect
Read
Ch1
Ch1
Ch1
5
4
3
Read
Ch4
Ch4
Ch4
7
6
5
Positive Mask Register Port 0/2
The Positive Mask Register for Port 0/2 (base + 18
register enables the Positive Edge Detect Register to capture low to high
transitions on individual channels. When a bit is set to "1" in this register it
enables that channel to be captured in the corresponding bit in the Positive Edge
Detect Register. When a bit is set to "0" it is disabled. If bit 4 of the
Control/Status Register is low ("0"), Port 0 data is accessed. If bit 4 is high ("1"),
Port 2 data will be accessed.
Positive Mask Register Port 0/2 (Channels 0-15/32-47) (base + 18h)
b + 18
15
14
h
Read/Wr
ite
Ch1
Ch1
Ch1
5
4
3
Read/Wr
ite
Ch4
Ch4
Ch4
7
6
5
Keysight E1459A/Z2404B User and SCPI Programming Guide
12
11
10
Ch1
Ch1
Ch1
Ch9
2
1
0
Ch4
Ch4
Ch4
Ch4
4
3
2
1
13
12
11
10
Ch1
Ch1
Ch1
2
1
0
Ch4
Ch4
Ch4
4
3
2
9
8
7
6
Ch8
Ch7
Ch6
Ch4
Ch3
Ch3
0
9
8
9
8
7
6
Ch9
Ch8
Ch7
Ch6
Ch4
Ch4
Ch3
Ch3
1
0
9
8
Keysight E1459A Register Definitions
) is read only. This
h
5
4
3
2
Ch5
Ch4
Ch3
Ch2
Ch3
Ch3
Ch3
Ch3
7
6
5
4
) can be read or written. This
h
5
4
3
2
Ch5
Ch4
Ch3
Ch2
Ch3
Ch3
Ch3
Ch3
7
6
5
4
1
0
Ch1
Ch0
Ch3
Ch3
3
2
1
0
Ch1
Ch0
Ch3
Ch3
3
2
95
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