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Keysight E1459A Register Definitions
Command Register Port 1/3
b + 20
15
14
13
h
Write
No Effect
Read
Always Returns FFF
98
The Command Register for Port 1/3 (base + 20
contains three bits used to control operating characteristics of the port. If bit 4 of
the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is high
("1"), Port 3 data will be accessed. The operation of these Command Registers is
identical to those of Port 0/2.
Command Register Port 1/3 (base + 20h)
12
11
10
9
h
For reading and writing, when BS = 0 in the Status/Control Register, the data for
Port 1 is accessed. When BS = 1, the data for Port 3 is accessed.
EDGE ENAB = "1" allows an edge interrupt (INTR for Port 1/3 to cause an
interrupt, if enabled in the Status/Control Register. When "0" edge interrupts
from Port 1/3 are disabled.
INT/EXT = "0" data will be latched using the internal clock. "1" data is latched
using EXT1/3 input.
DAV ENAB = "1" allows the DAV1/3 line to cause an interrupt if enabled in the
Status register. The DAV line is asserted when data is latched. This should only
be enabled when in external trigger mode. When set to "0" the DAV1/3 line
cannot cause an interrupt.
A potential hazard exists if software were to improperly program
the Keysight E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. In this situation, a DAV
interrupt would be posted each microsecond (if software were
able to service at that rate), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the Keysight E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected. (If bit 1 of the Command Register Word is set to a
one, then bit 2 must always be set to zero.)
In the Keysight E1459A the Data Ready Marker is guaranteed to
be cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker to
the control FPGA and will be lost.
8
7
6
5
4
3
1
Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions
) can be read or written. It
h
2
1
DAV ENAB
INT/EXT
DAV ENAB
INT/EXT
0
EDGE ENAB
EDGE ENAB
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