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Register Definitions
Channel Data Register Port 0/2
The Channel Data Register for Port 0/2 (base + 12
returns the current (last) data that has been clocked into the edge detection
circuitry based on either the internal or external trigger source. If bit 4 of the
Control/Status Register is low ("0"), Port 0 is accessed. If bit 4 is high ("1"), Port
2 data will be accessed.
Channel Data Register Port 0/2 (Channels 0-15/32-47) (base + 12h)
b +
15
14
13
12
h
Write
No Effect
Read
Ch1
Ch1
Ch1
5
4
3
Read
Ch4
Ch4
Ch4
7
6
5
Channels 0 through 15 are accessed when BS = 0 in the Status/Control Register.
Channels 32 through 47 are accessed when BS = 1 in the Status/Control
Register.
Keysight E1459A/Z2404B User and SCPI Programming Guide
A potential hazard exists if software were to improperly program
the Keysight E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. In this situation, a DAV
interrupt would be posted each microsecond (if software were
able to service at that rate), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the Keysight E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected. (If bit 1 of the Command Register Word is set to a
one, then bit 2 must always be set to zero.)
In the Keysight E1459A the Data Ready Marker is guaranteed to
be cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker to
the control FPGA and will be lost.
12
11
10
9
Ch1
Ch1
Ch1
Ch9
2
1
0
Ch4
Ch4
Ch4
Ch4
4
3
2
1
h
8
7
6
5
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch3
Ch3
0
9
8
7
Keysight E1459A Register Definitions
) is read only. This register
4
3
2
1
Ch4
Ch3
Ch2
Ch1
Ch3
Ch3
Ch3
Ch3
6
5
4
3
0
Ch0
Ch3
2
93
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