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Register Definitions
Channel Data Register Port 1/3
The Channel Data Register for Port 1/3 (base + 22
returns the current (last) data that has been clocked into the data capture
circuitry. If bit 4 of the Control/Status Register is low ("0"), Port 1 data is
accessed. If bit 4 is high ("1"), Port 3 data will be accessed. The operation of
these Channel Data Registers for Port 1/3 is identical to those of Port 0/2.
Channel Data Register Port 1/3 (Channels 16-31/48-63) (base + 22h)
b + 22
15
14
13
h
Write
No Effect
Read
Ch3
Ch3
Ch2
1
0
9
Read
Ch6
Ch6
Ch6
3
2
1
Channels 16 through 31 are accessed when BS = 0 in the Status/Control
Register. Channels 48 through 63 are accessed when BS = 1 in the
Status/Control Register.
Positive Edge Detect Register Port 1/3
The Positive Edge Detect Register for Port 1/3 (base + 24
the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is high
("1"), Port 3 data will be accessed. The operation of the Positive Edge Detect
Register for Port 1/3 is identical to those of Port 0/2.
Positive Edge Detect Register Port 1/3 (Channels 16-31/48-63) (base + 24h)
b + 24
15
14
13
h
Write
No Effect
Read
Ch3
Ch3
Ch2
1
0
9
Read
Ch6
Ch6
Ch6
3
2
1
For Positive/Negative Edge Detect and Mask Registers, channels 16 through 31
are accessed when BS = 0 in the Status/Control Register.
Keysight E1459A/Z2404B User and SCPI Programming Guide
12
11
10
9
Ch2
Ch2
Ch2
Ch2
8
7
6
5
Ch6
Ch5
Ch5
Ch5
0
9
8
7
12
11
10
9
Ch2
Ch2
Ch2
Ch2
8
7
6
5
Ch6
Ch5
Ch5
Ch5
0
9
8
7
Keysight E1459A Register Definitions
) is read only. This register
h
8
7
6
5
Ch2
Ch2
Ch2
Ch2
4
3
2
1
Ch5
Ch5
Ch5
Ch5
6
5
4
3
8
7
6
5
Ch2
Ch2
Ch2
Ch2
4
3
2
1
Ch5
Ch5
Ch5
Ch5
6
5
4
3
4
3
2
1
Ch2
Ch1
Ch1
Ch1
0
9
8
7
Ch5
Ch5
Ch5
Ch4
2
1
0
9
) is read only. If bit 4 of
h
4
3
2
1
Ch2
Ch1
Ch1
Ch1
0
9
8
7
Ch5
Ch5
Ch5
Ch4
2
1
0
9
0
Ch1
6
Ch4
8
0
Ch1
6
Ch4
8
99
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