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Installing and Configuring the E1459A
Input Debounce Processing
Each channel is debounced by a digital circuit specific to this function. Two
programmable clock sources establish reference parameters which determine
the debounce criteria for validating inputs. Channels are not independently
programmed for debounce period, but are instead grouped together in blocks of
32 channels per clock source. Channels 00-31 (Ports 0 and 1) are collectively
programmed via one clock source and channels 32-63 (Ports 2 and 3) are
programmed via a second clock source.
Programmable Debounce Parameters
Debounce circuits require that a channel input remain in a stable state for 4 to
4.5 periods of the programmable clock before a channel transition is declared.
The debounce clocks may be programmed for frequencies ranging from 250 KHz
down to 466 Hz. The 4 to 4.5 clock period requirements of the debouncers
translate into debounce periods which range from 16 S minimum to 9600
seconds (2.67 hours) maximum.
The debounce circuits can add considerable latency in the signal path and an
additional delay occurs within the Register FPGA. Normally the signals pass
though without significant delay. However, during a VXIbus transaction to this
port, the input signals are momentarily captured by a latch and are held for the
duration of the bus transaction plus 500 nS. This prevents data events from being
lost due to potential timing conflicts with VXIbus transactions. The data signals
are then synchronized with the system clock and synchronously captured in
either the data register, the positive edge event register, or the negative edge
event register. This can potentially add another 500 nS depending upon timing
circumstances.
Thus the input data is delayed by the debounce circuits, possibly by the input
latches (equal to bus transaction time plus 500 nS), and a synchronizing delay of
500 nS. The external clocks (front panel external trigger inputs) are also delayed
but by no more than 500 nS. Therefore, an external capture clock concurrent with
a data event will not capture the event unless consideration is given for data
latency.
The module has two primary modes of operation: the module can interrupt your
software when an event occurs or your software can periodically poll the module
to determine if an event has occurred. If the channel data registers are serviced
via a "polled mode" method (which is not keyed to the posting of the "marker
14
The user MUST ensure, based upon the programmed debounce
period and internal delays, that data to be captured has
propagated the debouncers and is fully setup prior to the
assertion of the externally generated capture clock.
Keysight E1459A/Z2404B User and SCPI Programming Guide
Functional Description
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