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Keysight E1459A Register Definitions
Positive Edge Detect Register Port 0/2
b + 14
15
14
h
Write
No Effect
Read
Ch1
Ch1
5
4
Read
Ch4
Ch4
7
6
94
The Positive Edge Detect Register for Port 0/2 (base + 14
register captures any low to high transitions with a "1" in this register for any
channel that has been enabled. A channel is enabled by setting a corresponding
bit in the Positive Mask Register. Once the register is read, the data is
automatically cleared. A transition is only seen if it is held long enough to pass
through the debouncers. If bit 4 of the Control/Status Register is low ("0"), Port 0
data is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Positive Edge Detect Register Port 0/2 (Channels 0-15/32-47) (base + 14h)
13
12
11
10
Ch1
Ch1
Ch1
Ch1
3
2
1
0
Ch4
Ch4
Ch4
Ch4
5
4
3
2
For Positive/Negative Edge Detect and Mask Registers, channels 0 through 15
are accessed when BS = 0 in the Status/Control Register.
For Positive/Negative Edge Detect and Mask Registers, channels 32 through 47
are accessed when BS = 1 in the Status/Control Register.
9
8
7
6
Ch9
Ch8
Ch7
Ch6
Ch4
Ch4
Ch3
Ch3
1
0
9
8
Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions
) is read only. This
h
5
4
3
2
Ch5
Ch4
Ch3
Ch2
Ch3
Ch3
Ch3
Ch3
7
6
5
4
1
0
Ch1
Ch0
Ch3
Ch3
3
2
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