Section Six; Theory Of Operation; Vmebus Interface; Data Lines - National Instruments Corporation GPIB-1014P User Manual

Section Six

Theory of Operation

This section discusses the major elements of the GPIB-1014P in detail with references to signals
and circuits shown in the schematic diagrams in Appendix B. However, a brief description of the
GPIB-1014P interface with a functional block diagram is provided in Section Two (see
Figure 2-4).
Signal names in the following discussion are referenced in terms of logic value (true or false, and
asserted or not asserted), and also in terms of logic level (TTL high or low). Both positive and
negative logic symbols are used in the schematic diagram. The terms clear, negate, unassert, reset,
and set false are synonymous as are set, assert, and set true. Since in the circuit implementation
some positive true signals are derived from the inverted output of flip-flops, these terms are not
synonymous with the device signals CLR (clear) and PR (preset).

VMEbus Interface

Low-power Schottky Transistor Transistor Logic (LSTTL), Advance Low-power Schottky
Transistor Transistor Logic (ALSTTL), or Fast Transistor Transistor Logic (FTTL) logic devices
buffer address, data, control, and status signals to or from the VMEbus. All drivers drive the
proper amount of current as required by the VMEbus specification, and all receivers meet the bus
loading limits as called out by the VMEbus specification.

Data Lines

An F245 octal bus transceiver connects VMEbus data lines D00 through D07 to the GPIB-1014P.
During interrupter Status/ID cycles or read cycles to the GPIB-1014P, the F245 is directed to allow
the GPIB-1014P to drive the data bus. During write cycles, the direction of the F245 is reversed to
allow the Talker, Listener, Controller (TLC) registers to receive data from the VME data bus. The
F245 transceiver is enabled when either the EV or the STB signal is high. The EV signal is
asserted to allow the interrupter to drive the data bus with a Status/ID byte while the STB signal is
asserted to enable the F245 during a data transfer cycle.

Control Signals

Note: An asterisk implies that the signal is active low.
The GPIB-1014P receives the VMEbus control signals DTACK*, DSO*, IACKIN*, and
WRITE* with LS240 buffers, while an ALS244 buffer receives DS1*, WRITE*, and AS*. The
slave monitors DTACK* to make certain the VME data bus has been released before beginning a
data transfer.
FTTL gates drive IRQ1* through IRQ7*, DTACK*, and IACKOUT*. The DTACK* and IRQ*
drivers have open-collector outputs. The GPIB-1014P does not drive the other control signals.
© National Instruments Corporation 6-1 GPIB-1014P User Manual