Hidden Registers; Internal Counter Register (Icr) - National Instruments Corporation GPIB-1014P User Manual

Table of Contents

Hidden Registers

The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is

loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred

to the hidden register. The hidden registers cannot be read, and in some cases the contents can only

be set; that is, they can be cleared or reset to initialized conditions only by issuing the Chip Reset

auxiliary command, or by a pon. Figure 4-2, earlier in this section, shows the five hidden registers

and illustrates how they are loaded with data from the AUXMR.

VMEbus Address:

AUXMR Control Code: 001 (Binary, Bits 7 - 5)

Attributes:

CLK3

Bit

Mnemonic

3-0w

CLK[3-0]

GPIB-1014P User Manual

Base Address + B (hex)

Write Only,

Accessed through AUXMR

CLK2

CLK1

Description

Reserved Bit

Write zero to this bit.

Clock Bits 3 though 0

The contents of the ICR are used to divide internal counters that generate

TLC state change delay times used by the IEEE-488 specification. The

most familiar of these times, T1, is the minimum delay between placing

the data or command bytes on the GPIB DIO lines and asserting DAV.

These delay times vary depending on the type of transfer in progress and

the value of the AUXRB bit TRI.

For proper operation, ICR should be set to eight because the TLC is

clocked at 8 MHz.

4-36

CLK0

Section Four

Table of Contents