Address Status Register (Adsr) - National Instruments Corporation GPIB-1014P User Manual

Section Four

Address Status Register (ADSR)

VMEbus Address:
Attributes:
7 6
CIC ATN*
The ADSR contains information that can be used to monitor the TLC GPIB address status.
Bit Mnemonic
7r CIC
6r ATN*
5r SPMS
4r LPAS
© National Instruments Corporation
Base Address + 9 (hex)
Read Only
5 4
LPAS
SPMS
Description
Controller-In-Charge Bit
CIC = -(CIDS + CADS)
CIC indicates that the TLC GPIB Controller function is in an active or
standby state, with ATN* on or off, respectively. The Controller
function is in an idle state, with ATN* off, if CIC=0.
Attention* Bit
ATN* is a status bit which indicates the current level of the GPIB ATN*
signal. If ATN* is 0, the GPIB ATN* signal is asserted.
Serial Poll Mode State Bit
If SPMS=1, the TLC GPIB Talker (T) or Talker Extended (TE) function
is enabled to participate in a serial poll. SPMS is set when the TLC has
been addressed as a GPIB Talker and the GPIB Active Controller has
issued the GPIB Serial Poll Enable (SPE) command message. SPMS is
cleared when the GPIB Serial Poll Disable (SPD) command is received,
by power on reset, or by issuing the Chip Reset auxiliary command.
Listener Primary Addressed State Bit
The LPAS bit is used when the TLC is configured for extended GPIB
addressing and, when set, indicates that the TLC has received its primary
listen address. In Mode 3, addressing (see Address Mode Register
Description), LPAS=1 indicates that the secondary address being
received on the next GPIB command may represent the TLC Extended
(Secondary) GPIB Listen address. LPAS is cleared by pon or by issuing
the Chip Reset auxiliary command.
3 2
TPAS
LA
4-21
Register Bit Descriptions
1 0
R
MJMN
TA
GPIB-1014P User Manual