National Instruments Corporation GPIB-1014P User Manual page 75

Register Descriptions
Bit Mnemonic
3w S
3w P[3-1]
Some examples of configuring the Parallel Poll Register are as follows:
Written to the AUXMR
7 6 5 4 3 2 1 0
0 1 1 1 0 0 0 0
0 1 1 0 0 0 0 0
0 1 1 0 1 0 0 1
GPIB-1014P User Manual
Description
Status Bit Polarity Bit
The S bit is used to indicate the polarity of the TLC local ist (individual
status) message. If S=1, the status is in phase, meaning that if, during a
Parallel Poll response, S=ist=1 and U=0, the TLC responds to the
Parallel Poll by driving one of the eight GPIB DIO lines low, thus
asserting it to a logic one. If S=1 and ist=0, the TLC does not drive the
DIO line.
If S=0, the status is in reverse phase, meaning that if, during a Parallel
Poll, ist=0, and U is 0, the TLC responds to the Parallel Poll by driving
one of the eight GPIB DIO lines low. If S=0 and ist=1, the TLC does
not drive the DIO line.
Refer to the description of AUXRB and the Set/Clear auxiliary
commands for more information.
Parallel Poll Response Bits 3 through 1
PPR bits 3 through 1, designated P[3-1], contain an encoded version of
the Parallel Poll Response. P[3-1] indicate which of the eight DIO lines
is asserted during a Parallel Poll (equal to N-1). The GPIB-1014P
normally drives the GPIB DIO lines using three-state drivers. During
Parallel Poll responses, however, the drivers automatically convert to
Open Collector mode, as required by IEEE-488. For example, if P[3-
1]=010 (binary), GPIB DIO line DIO3* is driven low (asserted) if the
GPIB-1014P is parallel polled (and S=ist).
Result
Unconfigures PPR
0 0 0 0 0 is written to the PPR. GPIB-1014P participates in a
Parallel Poll, asserting the DIO1 line if ist is 0. Otherwise,
the GPIB-1014P does not participate.
0 1 0 0 1 is written to the PPR. GPIB-1014P participates in a
Parallel Poll, asserting the DIO2 line if ist is 1. Otherwise,
the GPIB-1014P does not participate.
4-38
Section Four
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