Auxiliary Register E (Auxre) - National Instruments Corporation GPIB-1014P User Manual

Section Four

Auxiliary Register E (AUXRE)

VMEbus Address:
AUXMR Control Code: 110 (Binary, Bits 7 - 5)
Attributes:
4 3
0
0
Writing to Auxiliary Register E (AUXRE) is done via the AUXMR. Writing the binary value 110
into the Control Code (CNT[2-0]) and a bit pattern into the lower five bits (COM[4-0]) of the
AUXMR causes the two lowest order bits to be written to AUXRE. The 2-bit code, DHDC and
DHDT, determines how the TLC uses DAC Holdoff.
Bit Mnemonic
4-2w 0
1w DHDC
0w DHDT
© National Instruments Corporation
Base Address + B (hex)
Write Only,
Accessed through AUXMR
2 1
0 DHDC
Description
Reserved Bits
Write zeros to these bits.
DAC Holdoff on DCAS Bit
Setting DHDC enables DAC holdoff when the TLC enters Device Clear
Active State (DCAS). Clearing DHDC disables DAC Holdoff on
DCAS. Issuing the Finish Handshake auxiliary command releases the
Holdoff.
DAC Holdoff on DTAS Bit
Setting DHDT enables DAC holdoff when the TLC enters Device
Trigger Active State (DTAS). Clearing DHDT disables DAC Holdoff
on DTAS. Issuing the Finish Handshake auxiliary command releases
the Holdoff.
4-43
0
DHDT
W
Register Descriptions
GPIB-1014P User Manual