Address Register (Adr) - National Instruments Corporation GPIB-1014P User Manual

Section Four

Address Register (ADR)

VMEbus I/O Address:
Attributes:
7 6
ARS DT
The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both ADR0
and ADR1 must be loaded for all addressing modes.
Bit Mnemonic
7w ARS
6w DT
5w DL
4-0w AD5-1
© National Instruments Corporation
Base Address + D (hex)
Write Only, Internal to TLC
5 4
DL AD5
Description
Address Register Select Bit
ARS is 0 or 1 to select whether the seven lower-order bits of ADR must
be loaded into internal registers ADR0 or ADR1, respectively.
Disable Talker Bit
DT must be set if recognition of the GPIB talk address formed from
AD5 through AD1 (ADR[4-0]w) is not to be enabled.
Disable Listener Bit
DL must be set if recognition of the GPIB Listen address formed from
AD[5-1] is not to be enabled.
Address Bit
These bits specify the five low-order bits of the GPIB address that is to
be recognized by the TLC. (The corresponding GPIB Talk address is
formed by adding octal 100 to AD[5-1], while the corresponding GPIB
listen address is formed by adding octal 40.) The value written to AD[5-
1] must not be all ones; otherwise, the corresponding talk and listen
addresses would conflict with the GPIB Untalk (UNT) and Unlisten
(UNL) commands.
4-45
3 2
AD4 AD3
Register Descriptions
1 0
AD2 AD1
W
GPIB-1014P User Manual