Serial Poll Status Register (Spsr); Serial Poll Mode Register (Spmr) - National Instruments Corporation GPIB-1014P User Manual

Register Bit Descriptions

Serial Poll Status Register (SPSR)

VMEbus Address:
Attributes:

Serial Poll Mode Register (SPMR)

VMEbus Address:
Attributes:
7 6
S8 PEND
S8 rsv
Bit Mnemonic
7r,7w S8
5-0r S6-S1
5-0w
6r PEND
6w rsv
GPIB-1014P User Manual
Base Address + 7 (hex)
Read Only
Base Address + 7 (hex)
Write Only
5 4
S6 S5
S6 S5
Description
Serial Poll Status Byte
Cleared by Power On Reset (pon) and by issuing the Chip Reset
auxiliary command. These bits are used for sending device- or system-
dependent status information over the GPIB when the TLC is serial
polled. When the TLC is addressed as the GPIB Talker and receives the
GPIB multiline Serial Poll Enable (SPE) command message, it transmits
a byte of status information, SPMR[7-0], to the Controller-In-Charge
after the Controller goes to Standby and becomes an active Listener.
Pending Bit
PEND is set when rsv=1 and cleared when Negative Poll Response
States (NPRS) & Request Service (rsv) = 1. Reading the PEND status
bit can confirm that a request was accepted and that the Status Byte
(STB) was transmitted (PEND=0).
Request Service Bit
The rsv bit is used for generating the GPIB local request service
message. When rsv is set and the GPIB Active Controller is not serially
polling the TLC, the TLC enters the Service Request State (SRQS) and
asserts the GPIB SRQ signal. When the Active Controller reads the STB
during the poll, the TLC clears rsv at the Affirmative Poll Response State
(APRS). The rsv bit is also cleared by power on reset, LMR
(CFG2[1]w), and by issuing the Chip Reset auxiliary command.
3 2
S4 S3
S4 S3
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Section Four
1 0
R
S2 S1
S2 S1
W