National Instruments Corporation GPIB-1014P User Manual page 49

Register Bit Descriptions
Bit Mnemonic
3r DEC
3w DEC IE
2r ERR
2w ERR IE
GPIB-1014P User Manual
Description
Notes:
LACS: GPIB Listener Active State
EOI: GPIB End Or Identify Signal
EOS: GPIB End Of String message
REOS: Reception Of GPIB EOS allowed, AUXRA[2]w
ACDS: GPIB Accept Data State
pon: power on reset
Read ISR1: Bit is cleared immediately after it is read.
The END RX bit is set when the TLC is a Listener and the GPIB uniline
message, END, is received with a data byte from the GPIB Talker, or the
data byte in the DIR matches the contents of the End Of String Register
(EOSR).
Device Clear Bit
Device Clear Interrupt Enable Bit
DEC is set by:
DCAS
DEC is cleared by:
pon + (Read ISR1)
Notes:
DCAS: GPIB Device Clear Active State
pon: power on reset
Read ISR1: Bit is cleared immediately after it is read.
The DEC bit indicates that the GPIB Device Clear (DCL) command has
been received or that the GPIB Selected Device Clear (SDC) command
has been received while the TLC was a GPIB Listener (the TLC is in
DCAS).
Error Bit
Error Interrupt Enable Bit
ERR is set by:
TACS & SDYS & DAC & RFD + SIDS &
(Write CDOR) + (SDYS - SIDS)
ERR is cleared by:
pon + (Read ISR1)
4-12
Section Four
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