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National Instruments Corporation GPIB-1014P User Manual

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GPIB-1014P
User Manual
June 1994 Edition
Part Number 370944A-01
© Copyright 1984, 1994 National Instruments Corporation.
All Rights Reserved.

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Summary of Contents for National Instruments Corporation GPIB-1014P

  • Page 1 GPIB-1014P User Manual June 1994 Edition Part Number 370944A-01 © Copyright 1984, 1994 National Instruments Corporation. All Rights Reserved.
  • Page 2 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203 (512) 794-5678 Branch Offices: Australia (03) 879 9422, Austria (0662) 435986, Belgium 02/757.00.20, Canada (Ontario) (519) 622-9310, Canada (Québec) (514) 694-8521, Denmark 45 76 26 00, Finland (90) 527 2321, France (1) 48 14 24 24, Germany 089/741 31 30, Italy 02/48301892, Japan (03) 3788-1921, Mexico 95 800 010 0793, Netherlands 03480-33466, Norway 32-84 84 00, Singapore 2265886, Spain (91) 640 0085, Sweden 08-730 49 70, Switzerland 056/20 51 51, Taiwan 02 377 1200, U.K.
  • Page 3 Limited Warranty The GPIB-1014P is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
  • Page 4 FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies: Federal Communications Commission This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital...
  • Page 5 Preface The GPIB-1014P is a single-height circuit board which interfaces the VMEbus to the IEEE-488 General Purpose Interface Bus (GPIB). The GPIB-1014P provides a means to implement VMEbus test and measurement systems with standard interconnecting cables. Organization of the Manual This manual describes the mechanical and electrical aspects of the GPIB-1014P and contains information concerning its operation and programming.
  • Page 6 The following abbreviations are used in the text of this manual. ampere Celsius ° degree hexadecimal inch kbytes 1000 bytes meter Mbytes million bytes millimeter megahertz µsec microsecond nsec nanosecond second volt volts direct current GPIB-1014P User Manual © National Instruments Corporation...
  • Page 7 To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix G, Customer Communication, at the end of this manual. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 8: Table Of Contents

    VMEbus Slave-Data ..................2-3 Interrupter ......................2-4 VMEbus Modules Not Provided ............... 2-5 Diagnostic Aids ....................2-5 Data Transfer Features ....................2-5 GPIB-1014P Functional Description ................2-5 Section Three Configuration and Installation ..................3-1 Configuration ........................ 3-1 Access Mode ..................... 3-3 VMEbus Base Address ..................
  • Page 9 Going from Standby to Active Controller ............5-4 Going from Active to Idle Controller ............... 5-4 The GPIB-1014P as GPIB Talker and Listener ............5-5 Programmed Implementation of Talker and Listener ........5-5 Addressed Implementation of the Talker and Listener ........5-5 Address Mode 1 ..................
  • Page 10 Timing Control Logic ....................6-3 Interrupter Logic ......................6-3 GPIB Interface ......................6-4 Test and Troubleshooting ....................6-5 Section Seven GPIB-1014P Diagnostic and Troubleshooting Test Procedures ..... 7-1 Interpreting Test Procedures ..................7-1 GPIB-1014P Hardware Installation Tests ..............7-2 Appendix A Specifications ........................
  • Page 11 Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities ............. 2-10 Table 2-4. GPIB-1014P IEEE-1014 Interrupter Compliance Levels ........2-12 Table 3-1. GPIB-1014P Pin Assignment on VMEbus Connector P1 ........3-9 Table 4-1. GPIB-1014P Register Map .................. 4-1 Table 4-2. Clues to Understanding Mnemonics ..............4-3 Table 4-3.

  • Page 12: Section One

    Section One General Information The GPIB-1014P is an IEEE-488 interface for the VMEbus. This interface permits IEEE-488 compatible engineering, scientific, or medical instruments to be controlled from a VMEbus-based computer. The GPIB-1014P has the following features: Complete IEEE-488 Talker/Listener/Controller (TLC) capability using the NEC µPD7210 •...

  • Page 14: What Your Kit Should Contain

    Unpacking Follow these steps when unpacking your GPIB-1014P: 1. Your GPIB-1014P board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, touch the plastic bag to a metal part of your VMEbus computer chassis before removing the board from the bag.

  • Page 15: Section Two

    The GPIB-1014P measures 160 by 100 mm and is supplied with a standard 24-pin GPIB connector mounted on the front panel. The card is available with both single- and double-height metal front panels (.8 in. width). A DIN 41612 96-pin connector connects the GPIB-1014P to the VMEbus backplane.

  • Page 16: Vmebus Characteristics

    Table 2-3 later in this section summarizes the capabilities of these modules. VMEbus Slave-Addressing The GPIB-1014P occupies 16 bytes of consecutive memory addresses located in the A16 (short) Input/Output (I/O) space. These addresses are used to access the GPIB Talker/Listener/Controller (TLC).

  • Page 17: Vmebus Slave-Data

    8 bits VMEbus Slave-Data As discussed previously, the GPIB-1014P can function as a VMEbus slave, decoding memory addresses and commands from a VMEbus master. It is designed to accommodate address pipelining as well as Address Only (ADO) cycles. All data is transferred to and from the VMEbus with lines D00 through D07.

  • Page 18: Interrupter

    Upon seeing DS0* high, the interrupter releases the data bus and the interrupt request line. This implies that the GPIB-1014P interrupter is a Release On Acknowledge (ROAK) interrupter. Note: Even though the interrupt request line is no longer driven, the TLC Interrupt (INT) line remains asserted until it is cleared in the interrupt service routine by reading the appropriate status register (ISR1 or ISR2).

  • Page 19: Vmebus Modules Not Provided

    Section Two General Description VMEbus Modules Not Provided Because the GPIB-1014P is not designed to be VMEbus System Controller, it does not have the following modules: • Master • Bus Timer • Arbiter • Interrupt Handler • IACK Daisy Chain Driver •...

  • Page 20: Figure 2-1. Gpib-1014P With A Vmebus Computer

    General Description Section Two Figure 2-1 and Figure 2-2 show typical applications for the GPIB-1014P. In Figure 2-2, the GPIB-1014P is used to interface an assortment of test instruments to a VMEbus computer system, which then functions as an intelligent System Controller. This is the traditional role of the GPIB.

  • Page 21: Figure 2-2. Gpib-1014P In A Multiprocessor Application

    Bus Extender Up to 300 Meters (RS-422) Computer Center GPIB-100 Bus Extender Production & Testing PDP 11/44 with GPIB11-2 S-100 Computer IEEE-488 Interface GPIB-696P IEEE-488 Interface Figure 2-2. GPIB-1014P in a Multiprocessor Application © National Instruments Corporation GPIB-1014P User Manual...
  • Page 22 AM5-AM0 A15-A01 A03-A01 Bus Address LWORD* Decoding DSO* AS*, IACK* 75160A Transceiver WRITE* Timing and DI08*- µPD7210 Data DI01* DTACK* Direction 75162A DS1* Control Transceiver SRQ*, ATN* IACKIN* EOI*, DAV* Interrupt IACKOUT* NRFD*, NDAC* Logic IFC*, REN* IRQ1*- IRQ7* System Data Bus Controller Transceivers...
  • Page 23 Monitors the VMEbus utility signals to generate the 8 MHz clock used by the TLC and to detect System Reset. • Timing State Machine Controls the timing of accesses to the GPIB-1014P from the VMEbus. • Interrupter Implements the correct VMEbus priority interrupt protocol, allowing the GPIB-1014P to request and respond to an interrupt acknowledge cycle.

  • Page 24: Table 2-3. Gpib-1014P Ieee-488 Interface Capabilities

    General Description Section Two Table 2-3 lists the capabilities of the GPIB-1014P in terms of the IEEE-488 standard codes. Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities Capability Code Description Complete Source Handshake capability Complete Acceptor Handshake capability DAC and RFD Holdoff on certain events...
  • Page 25 Listener or Extended Listener. It can be placed in a Listen Only mode, and it is unaddressed to listen when it receives its talk address. The GPIB-1014P has full capabilities for requesting service from another Controller. It can be placed in local mode, but the interpretation of remote versus local mode is software-dependent.
  • Page 26 General Description Section Two capability, but the interpretation is software dependent. All Controller functions as specified by the IEEE-488 standard are included in the GPIB-1014P. These include the capability to: • Be System Controller • Initialize the interface • Send Remote Enable •...

  • Page 27: Section Three

    This section describes the configuration and installation of the GPIB-1014P. Configuration Before installing the GPIB-1014P in the VMEbus backplane, the following options must be configured with hardware jumpers or switches that are located on the GPIB-1014P interface board: • Access Mode (W2) •...

  • Page 29: Access Mode

    3-2a. To configure the board for non-privileged access, place the jumper on the side labeled NP as shown in Figure 3-2b. The default setting for the GPIB-1014P is for non-privileged access. In the Supervisor (privileged) mode, the GPIB-1014P only responds to Address Modifier (AM) code 2D.

  • Page 30: Figure 3-3. Configuration For Vmebus Base Address 1000 Hex (Default Setting)

    This side down for logic 1 This side down for logic 0 This side down for logic 1 This side down for logic 0 Figure 3-3. Configuration for VMEbus Base Address 1000 hex (default setting) GPIB-1014P User Manual © National Instruments Corporation...

  • Page 31: Vmebus Interrupt Configuration

    Configuration and Installation VMEbus Interrupt Configuration The GPIB-1014P contains circuitry that permits it to request service by driving one of the VMEbus interrupt request lines. The GPIB-1014P responds to an interrupt acknowledge cycle of correct priority by providing an 8-bit vector (status byte) that is used to locate the appropriate interrupt service routine.

  • Page 32: Figure 3-5. Vmebus Interrupt Priority Code Selection

    This side down for logic 0 a. Switch configuration using IRQ2* (Default setting) This side down for logic 1 This side down for logic 0 b. Switch configuration using IRQ4* Figure 3-5. VMEbus Interrupt Priority Code Selection GPIB-1014P User Manual © National Instruments Corporation...

  • Page 33: Interrupt Status/Id Vector Selection

    1A hex. = the side you press down for Status/ID Byte 1A hex This side down for logic 1 This side down for logic 0 Figure 3-6. Status/ID Byte 1A hex © National Instruments Corporation GPIB-1014P User Manual...

  • Page 34: Gpib Cable Shield Grounding

    Place the jumper on the side labeled ISO to leave the GPIB cable shield isolated. Select one configuration depending on whether or not the GPIB-1014P is the GPIB System Controller and whether or not the GPIB cable shield is grounded elsewhere. Figure 3-7 shows the two possible configurations.

  • Page 35: Installation

    Configuration and Installation Installation The GPIB-1014P is a single-height board that interfaces to the VMEbus P1 and is available with either a single- or double-height metal front cover plate. The following paragraphs describe the GPIB-1014P interface to the VMEbus backplane and to the IEEE-488 bus.

  • Page 36: Verification Testing

    Optional cables are available to connect the GPIB-1014P to other GPIB devices. Connect the cable to the GPIB-1014P at the standard GPIB connector labeled J1 at the top of the interface board. (The GPIB connector protrudes through the metal front cover plate.)

  • Page 37: Figure 3-8. Gpib Cable Connector

    GND (TW PAIR W/NRFD*) NDAC* GND (TW PAIR W/NDAC*) IFC* GND (TW PAIR W/IFC*) SRQ* GND (TW PAIR W/SRQ*) ATN* GND (TW PAIR W/ATN*) SHIELD SIGNAL GROUND Figure 3-8. GPIB Cable Connector © National Instruments Corporation 3-11 GPIB-1014P User Manual...

  • Page 38: Section Four

    Register Map The register map for the GPIB-1014P is shown in Table 4-1. This table gives the register name, the register address, the type of the register, and the size of the register in bits. Table 4-1. GPIB-1014P Register Map...

  • Page 39: Register Sizes

    All program registers on the GPIB-1014P are 8-bit registers. Register Description Format The remainder of this section discusses each of the GPIB-1014P registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register.

  • Page 40: Table 4-2. Clues To Understanding Mnemonics

    4 letters, Interface function as defined in the ends in S IEEE-488 standard Ends in R, R0, R1, R2 GPIB program register 3 letters, uppercase Remote GPIB message 3 letters, lowercase Local GPIB message © National Instruments Corporation GPIB-1014P User Manual...

  • Page 41: Interface Registers

    All are located within the NEC µPD7210 Talker/Listener/Controller (TLC) integrated circuit. Each of the 16 interface registers is addressed relative to the GPIB-1014P VMEbus base address which is set with DIP switches (refer to Base Address in Section Three).

  • Page 42: Figure 4-1. Μpd7210 Interface Registers

    AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 ADR0 ADR1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 EOSR Note: X indicates a don't care bit. Figure 4-1. µPD7210 Interface Registers © National Instruments Corporation GPIB-1014P User Manual...

  • Page 43: Figure 4-2. Writing To The Hidden Registers

    CLK1 CLK0 PPR is loaded with: AUXRA is loaded with: XEOS REOS HLDE HLDA AUXRB is loaded with: SPEOI ENABLE AUXRE is loaded with: DHDT DHDC Figure 4-2. Writing to the Hidden Registers GPIB-1014P User Manual © National Instruments Corporation...

  • Page 44: Data In Register (Dir)

    DI0 is the least significant bit of the data byte and corresponds to GPIB DIO1. DI7 is the most significant bit of the data byte and corresponds to GPIB DIO8. Mnemonic Description 7-0r DIR[7-0] Data In Bits 7 through 0 © National Instruments Corporation GPIB-1014P User Manual...

  • Page 45: Command/Data Out Register (Cdor)

    CDOR, the TLC GPIB Source Handshake (SH) function is initiated and the byte is transferred to the GPIB. Mnemonic Description 7-0w CDO[7-0] Command/Data Out Bits 7 through 0 GPIB-1014P User Manual © National Instruments Corporation...

  • Page 46: Interrupt Status Register 1 (Isr1)

    + (Read ISR1) Notes: UCG: GPIB Universal Command Group message ACG: GPIB Addressed Command Group message TADS: GPIB Talker Addressed State LADS: GPIB Listener Addressed State defined: GPIB command automatically recognized and executed by TLC © National Instruments Corporation GPIB-1014P User Manual...
  • Page 47 ADM1 & ADM0 & (TPAS + LPAS) & SCG & ACDS APT is cleared by: pon + (Read ISR1) Notes: ADM1: Address Mode Register bit 1, ADMR[1]w ADM0: Address Mode Register bit 0, ADMR[0]w GPIB-1014P User Manual 4-10 © National Instruments Corporation...
  • Page 48 End Received Bit END IE End Received Interrupt Enable Bit END RX is set by: LACS & (EOI + EOS & REOS) & ACDS END RX is cleared by: pon + (Read ISR1) © National Instruments Corporation 4-11 GPIB-1014P User Manual...
  • Page 49 Error Interrupt Enable Bit ERR is set by: TACS & SDYS & DAC & RFD + SIDS & (Write CDOR) + (SDYS - SIDS) ERR is cleared by: pon + (Read ISR1) GPIB-1014P User Manual 4-12 © National Instruments Corporation...
  • Page 50 GPIB Talker. The DO bit is cleared when a byte is written to the CDOR and also when the TLC ceases to be the Active Talker. Data In Bit DI IE Data In Interrupt Enable Bit DI is set by: LACS & ACDS & -(Continuous Mode) © National Instruments Corporation 4-13 GPIB-1014P User Manual...
  • Page 51 Finish Handshake: Finish Handshake auxiliary command issued Holdoff Mode: RFD holdoff state Read DIR: Read Data In Register The DI bit indicates that the TLC, as a GPIB Listener, has accepted a data byte from the GPIB Talker. GPIB-1014P User Manual 4-14 © National Instruments Corporation...

  • Page 52: Interrupt Status Register 2 (Isr2)

    (DO & DO IE) + (DI & DI IE) + (SRQI & SRQI IE) + (REMC & REMC IE) + (CO & CO IE) + (LOKC & LOKC IE) + (ADSC & ADSC IE) © National Instruments Corporation 4-15 GPIB-1014P User Manual...
  • Page 53 (CIC & SRQ & -(RQS & DAV)) becomes true SRQI is cleared by: pon + (Read ISR2) Notes: CIC: GPIB Controller In Charge SRQ: GPIB Service Request message RQS: GPIB Request Service message DAV: GPIB Data Valid message GPIB-1014P User Manual 4-16 © National Instruments Corporation...
  • Page 54 Bit is cleared immediately after it is read. CO = 1 indicates CDOR is empty and that another command can be written to it for transmission to the GPIB without overwriting a previous command. © National Instruments Corporation 4-17 GPIB-1014P User Manual...
  • Page 55 ADSC is set by: [(any change in TA) + (any change in LA) + (any change in CIC) + (any change in MJMN)] & -(lon + ton) ADSC is cleared by: pon + (Read ISR2) GPIB-1014P User Manual 4-18 © National Instruments Corporation...
  • Page 56 Read ISR2: Bit is cleared immediately after it is read. ADSC is set whenever there is a change in one of the four bits: TA, LA, CIC, MJMN of the Address Status Register (ADSR). © National Instruments Corporation 4-19 GPIB-1014P User Manual...

  • Page 57: Serial Poll Status Register (Spsr)

    TLC clears rsv at the Affirmative Poll Response State (APRS). The rsv bit is also cleared by power on reset, LMR (CFG2[1]w), and by issuing the Chip Reset auxiliary command. GPIB-1014P User Manual 4-20 © National Instruments Corporation...

  • Page 58: Address Status Register (Adsr)

    Description), LPAS=1 indicates that the secondary address being received on the next GPIB command may represent the TLC Extended (Secondary) GPIB Listen address. LPAS is cleared by pon or by issuing the Chip Reset auxiliary command. © National Instruments Corporation 4-21 GPIB-1014P User Manual...

  • Page 59: Address Mode Register (Admr)

    MJMN bit indicates which, if either, of the TLC Talker/Listener functions is addressed or active. MJMN is always zero unless a dual primary addressing mode (Mode 1 or Mode 3) is enabled (see Address Mode Register later in this section). GPIB-1014P User Manual 4-22 © National Instruments Corporation...
  • Page 60 Transmit/Receive Mode Bits 1 through 0 TRM1 and TRM0 control the function of the TLC T/R2 and T/R3 output pins in the following manner: TRM1 TRM0 T/R2 T/R3 EOI OE TRIG TRIG EOI OE © National Instruments Corporation 4-23 GPIB-1014P User Manual...
  • Page 61 In this manner, mode 2 addressing uses the Extended Talker and Extended Listener functions as defined in IEEE- 488, without requiring computer program intervention. In mode 2, ADR0 and ADR1 contain the TLC primary and secondary GPIB addresses, respectively. GPIB-1014P User Manual 4-24 © National Instruments Corporation...
  • Page 62 AUXMR, signaling a valid or invalid secondary address, respectively, to the TLC. ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set. © National Instruments Corporation 4-25 GPIB-1014P User Manual...

  • Page 63: Command Pass Through Register (Cptr)

    Non-Valid auxiliary command is written to the AUXMR. Table 4-3. Multiline GPIB Commands Recognized by the µPD7210 Hex Number Message Description Go To Local Selected Device Clear Parallel Poll Configure Group Execute Trigger (continues) GPIB-1014P User Manual 4-26 © National Instruments Corporation...
  • Page 64 The CPTR is read during a TLC-initiated Parallel Poll operation to fetch the Parallel Poll response. The PPR message is latched into the CPTR when CPPS is set, until CIDS is set, or until a command byte is sent over the GPIB. © National Instruments Corporation 4-27 GPIB-1014P User Manual...

  • Page 65: Auxiliary Mode Register (Auxmr)

    COM[4-0] is to be used). If CNT[2-0] are all zero, then the special command selected by COM[4-0] is executed; otherwise, the hidden register selected by CNT[2-0] is loaded with the data from COM[4-0]. GPIB-1014P User Manual 4-28 © National Instruments Corporation...

  • Page 66: Table 4-4. Auxiliary Command Summary

    Set Paralle l Poll Flag 1 0 0 0 1 Take Control Asynchronously (Pulsed) 1 0 0 1 0 Take Control Synchronously 1 1 0 1 0 Take Control Synchronously on End (continues) © National Instruments Corporation 4-29 GPIB-1014P User Manual...
  • Page 67 Set REN 1 0 1 1 1 Clear REN 1 0 1 0 0 Disable System Control * CNT[2-0] set to 000 binary ** Represents all eight bits of the Auxiliary Mode Register GPIB-1014P User Manual 4-30 © National Instruments Corporation...
  • Page 68 • The contents of the ICR is set to eight (F3 set to 1; F2, F1, and F0 set to 0). • The TRM0 bit and the TRM1 bit are cleared. (continues) © National Instruments Corporation 4-31 GPIB-1014P User Manual...
  • Page 69 Holdoff on RFD or DAC. 0 0 1 0 0 Trigger Note: Trigger cannot be used with the GPIB-1014P. The Trigger command generates a high pulse on the TRIG pin (T/R3 pin when TRM1=0) of the TLC. The Trigger command performs the same function as if the DET (Device Trigger) bit (ISR1[5]r) were set.
  • Page 70 Controller Active State (CACS) or when it enters CACS. When the TLC leaves CACS, gts is cleared. 1 0 0 0 1 Take Control Asynchronously The Take Control Asynchronously command pulses the local message tca. (continues) © National Instruments Corporation 4-33 GPIB-1014P User Manual...
  • Page 71 Listen auxiliary command is issued or the TLC enters the Listener Idle State (LIDS). 1 1 1 0 0 Local Unlisten The Local Unlisten command generates the local message lun in the form of a pulse. (continues) GPIB-1014P User Manual 4-34 © National Instruments Corporation...
  • Page 72 These commands generate the local message request system control (rsc) and set Interface Clear (IFC) to the value of COM3. These commands should only be issued if the GPIB-1014P is the System Controller (SC). In order to meet the IEEE-488 requirements, you must not issue for at least 100 µsec.

  • Page 73: Hidden Registers

    These delay times vary depending on the type of transfer in progress and the value of the AUXRB bit TRI. For proper operation, ICR should be set to eight because the TLC is clocked at 8 MHz. GPIB-1014P User Manual 4-36 © National Instruments Corporation...

  • Page 74: Parallel Poll Register (Ppr)

    PPE message, and the I/O write operation (to the PPR) is the same as the receipt of the PPE message from the GPIB Controller. When U=1, S and P3-1 do not carry any meaning, but they must be cleared. © National Instruments Corporation 4-37 GPIB-1014P User Manual...
  • Page 75 Unconfigures PPR 0 1 1 0 0 0 0 0 0 0 0 0 0 is written to the PPR. GPIB-1014P participates in a Parallel Poll, asserting the DIO1 line if ist is 0. Otherwise, the GPIB-1014P does not participate.

  • Page 76: Auxiliary Register A (Auxra)

    EOS message when the TLC is in Listener Active State (LACS). If REOS is set and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set. © National Instruments Corporation 4-39 GPIB-1014P User Manual...
  • Page 77 Holdoff. The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer (no data reception). In continuous mode, the DI bit (ISR1[0]r) is not set by the reception of a data byte. GPIB-1014P User Manual 4-40 © National Instruments Corporation...

  • Page 78: Auxiliary Register B (Auxrb)

    The INV bit affects the polarity of the TLC INT pin. Setting INV causes the polarity of the Interrupt (INT) pin on the TLC to be active low. As implemented on the GPIB-1014P, configuring the INT pin to active low results in interrupt request errors. Consequently, INV should always be clear and should never be set.
  • Page 79 DAC message is held and the Handshake stops until the Valid auxiliary command is issued. The undefined command can be read from the CPTR and processed by the software. GPIB-1014P User Manual 4-42 © National Instruments Corporation...

  • Page 80: Auxiliary Register E (Auxre)

    DAC Holdoff on DTAS Bit Setting DHDT enables DAC holdoff when the TLC enters Device Trigger Active State (DTAS). Clearing DHDT disables DAC Holdoff on DTAS. Issuing the Finish Handshake auxiliary command releases the Holdoff. © National Instruments Corporation 4-43 GPIB-1014P User Manual...

  • Page 81: Address Register 0 (Adr0)

    These are the lower five bits of the TLC GPIB primary (or major) address. (The primary talk address is formed by adding octal 100 to AD5-0 through AD1-0, while the listen address is formed by adding octal 40.) GPIB-1014P User Manual 4-44 © National Instruments Corporation...

  • Page 82: Address Register (Adr)

    40.) The value written to AD[5- 1] must not be all ones; otherwise, the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and Unlisten (UNL) commands. © National Instruments Corporation 4-45 GPIB-1014P User Manual...

  • Page 83: Address Register 1 (Adr1)

    The secondary address is formed by adding hex A0 to bits AD[5-1 – 1-1]. The minor talk address is formed by adding hex 40 to AD[5-1 – 1- 1], while the listen address is formed by adding a hex 20. GPIB-1014P User Manual 4-46 © National Instruments Corporation...

  • Page 84: End Of String Register (Eosr)

    XEOS bit of AUXRA is set, the END message (GPIB EOI* line asserted low) is sent along with the data byte whenever the contents of the CDOR matches the EOSR. Mnemonic Description 7-0w EOS7- End of String Bits 7 through 0 EOS0 © National Instruments Corporation 4-47 GPIB-1014P User Manual...

  • Page 85: Section Five

    Programming Considerations This section explains important considerations for programming the GPIB-1014P. Initialization On power-up (pon), the VMEbus system typically issues a system reset (SYSRESET*) that drives the GPIB-1014P RESET* signal active and initializes the following circuitry: • Timing State Machine •...

  • Page 86: The Gpib-1014P As Gpib Controller

    8.Execute the desired TLC auxiliary commands. The GPIB-1014P as GPIB Controller The GPIB-1014P Controller function is generally in one of two modes: idle or in charge. When in charge, the Controller function is either active (asserting ATN) or standby (not asserting ATN). The following paragraphs discuss the various transitions between these two modes.

  • Page 87: Sending Remote Multiline Messages (Commands)

    Section Five Programming Considerations Another Active Controller passes control to the GPIB-1014P by sending the TLC GPIB talk address (MTA) followed by the GPIB Take Control (TCT) message. The TLC, upon receiving these two messages (MTA and TCT), automatically becomes CIC when ATN is dropped. The exact sequence of events is as follows: 1.

  • Page 88: Going From Standby To Active Controller

    In Cases 2 and 3, the END IE bit in IMR1 can also be set to indicate to the program that the TLC (functioning as a GPIB Listener) has received its last byte. In all cases, a CO status indicates that the GPIB-1014P is now Active Controller. GPIB-1014P User Manual...

  • Page 89: Going From Active To Idle Controller

    3. As soon as the TCT command message is accepted by all devices on the GPIB, the TLC automatically unasserts ATN and the new Controller asserts ATN. The GPIB-1014P as GPIB Talker and Listener The TLC can be either GPIB Talker or Listener, but not both simultaneously. Either function is deactivated automatically if the other is activated.

  • Page 90: Address Mode 1

    Determine whether the command just received is a listen, talk, major, or minor address by reading the LPAS, TPAS, and MJMN bits of the ADSR. • Read the secondary address in the CPTR and determine whether or not it is the address of the TLC. GPIB-1014P User Manual © National Instruments Corporation...

  • Page 91: Sending/Receiving Messages

    To send data, wait until the GPIB-1014P has been programmed or addressed to talk and the CDOR is empty. When this occurs, the DO bit in the ISR1 is set, indicating that it is safe to write a byte to the CDOR.

  • Page 92: Sending/Receiving End Or Eos

    Interrupts The interrupt circuitry of the GPIB-1014P allows the board to interrupt the CPU to request service. Prior to use, the following three characteristics of the interrupter must be set (see Interrupt Request Line Selection in Section Three for details): •...

  • Page 93: Responding To A Serial Poll

    CIC asserts ATN to terminate the poll. The GPIB EOI line is asserted along with the status byte (that is, the END message is sent) during the serial poll if bit B1 of the AUXRB is set. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 94: Parallel Polls

    GPIB address. Thus, one device might be assigned to respond with remote message PPR1 (driving DIO1), while a GPIB-1014P User Manual 5-10 © National Instruments Corporation...

  • Page 95: Responding To A Parallel Poll

    Responding To a Parallel Poll Before the GPIB-1014P can be polled by the CIC, the TLC must be configured either locally by your program at initialization time or remotely by the CIC. Configuration involves the following: •...

  • Page 96: Section Six

    During interrupter Status/ID cycles or read cycles to the GPIB-1014P, the F245 is directed to allow the GPIB-1014P to drive the data bus. During write cycles, the direction of the F245 is reversed to allow the Talker, Listener, Controller (TLC) registers to receive data from the VME data bus. The F245 transceiver is enabled when either the EV or the STB signal is high.

  • Page 97: Address Lines

    The clocked output signal is labeled MCYC. If MCYC is false, the GPIB-1014P is prevented from taking any action until a new address cycle begins. If MCYC is true, the GPIB-1014P is able to respond if DS0* goes low. DS1* is not monitored for the purpose of distinguishing 16-bit transfers from 8-bit transfers, so the GPIB-1014P responds to BYTE (0-1) or BYTE (2-3) accesses.

  • Page 98: Clock And Reset Circuitry

    GPIB-1014P), the GPIB-1014P waits for DTACK* to be released and for DS0* to be asserted. The GPIB-1014P then asserts STRT after delaying a minimum of 85 nsec in order to meet the TLC address set-up time.

  • Page 99: Gpib Interface

    (DEN*=1), IDTACK* is high, and DS1* is released. If the address lines A01 through A03 do not match the indicated priority of the GPIB-1014P, the Q* output of the flip-flop is latched high, indicating that IACKOUT* is to be asserted. After IACKIN and the delayed AS are received high, the VMEbus signal IACKOUT* is driven low.
  • Page 100 T/R3 is high when the three-state driver mode is active and low when the open collector mode is active. When the GPIB-1014P is parallel polled, the transceiver switches to open collector mode. SC is set whenever the System Controller Select logic senses that the TLC has received the Set IFC auxiliary command;...

  • Page 101: Test And Troubleshooting

    Section Six Test and Troubleshooting The GPIB-1014P is designed to aid acceptance testing and troubleshooting of either hardware failures or software bugs. The hardware provides several features that enable stand-alone testing. The NDAC* and DIO1* bits can be used to determine if the output signals of the TLC, the 75160A, and the 75162A are functioning properly.

  • Page 102: Section Seven

    The tests should be performed without connecting the GPIB-1014P to another GPIB device. All GPIB cables should be removed. If the GPIB-1014P does not perform as described in the test procedures, users are advised to carefully perform the following steps.

  • Page 103: Gpib-1014P Hardware Installation Tests

    Diagnostics and Troubleshooting Section Seven GPIB-1014P Hardware Installation Tests 1. Initialize TLC. AUXMR = 2 Chip Reset AUXMR = 0 Immediate execute pon 2. Send Chip Reset, then read registers and compare to reset values. AUXMR = 2 Chip Reset...
  • Page 104 Immediate execute pon AUXMR = 1E set IFC AUXMR = 16 clear IFC ADSR = 80? ISR2 = 9? CO + ADSC AUXMR = 10 go to standby ADSR = C0? CIC + ATN* © National Instruments Corporation GPIB-1014P User Manual...

  • Page 105: Appendix A Specifications

    6.3 x 3.9 in. Input/output connector IEEE-488 standard 24-pin Operating Environment Component temperature 0° to 70° C Relative humidity 10% to 90% noncondensing Storage Environment Temperature -62° to 71° C Relative humidity 0% to 100% noncondensing © National Instruments Corporation GPIB-1014P User Manual...

  • Page 106: Parts List And Schematic Diagrams

    Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB-1014P. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 117: Appendix C Sample Programs

    • Pass GPIB control to another device (PASSC). Assumptions regarding the state of the GPIB-1014P appear at the beginning of each routine and must be adhered to for proper, error-free operation. The following characteristics of the code must be considered: •...
  • Page 118 CSEND (Command Send) (Write Commands) PASSC (Pass Control) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 68000 Code BASE 0xFF1000 | Base address of GPIB-1014P interface BASE + 0x1 | Data In Register (read) CDOR BASE + 0x1 | Control/Data Out Register (write) ISR1 BASE + 0x3...
  • Page 119 | ADSR Bits NATN 0100 | Not ATN | ADMR Bits MODE1 = | Address Mode 1 | GPIB-1014P functions for T/R2 and T/R3 | AUXMR Hidden Registers | Internal Counter Register 0140 | Parallel Poll Register AUXRA = 0200...
  • Page 120 | REN flag (zero to not set REN, non-zero to set REN) tctadr: .byte | TCT address of new Active Controller vseoi: .byte | SEOI flag (zero to not send, non-zero to send | END message with last DSEND byte) GPIB-1014P User Manual © National Instruments Corporation...
  • Page 121 | Status on return: - The following registers are cleared: ISR1/2, IMR1/2, SPMR, SPSR, PPR, AUXRA, AUXRE - Other registers are configured as described - The GPIB-1014P interface functions are reset to idle and are enabled © National Instruments Corporation GPIB-1014P User Manual...
  • Page 122 | T/R signal mode movb #MA+SEL0,ADR.L | Set GPIB address (mode 1 primary only), with | Talker/Listener enabled movb #DT1+DL1+SEL1,ADR.L | Disable secondary address recognition movb #ICR+8,AUXMR.L | Set clock divider for 8MHz, low speed GPIB-1014P User Manual © National Instruments Corporation...
  • Page 123 | * * * * * * * * * * * * * * * * * * * * * * | Summary: - Initialize the interface function of other GPIB devices | Assumptions on entry: - GPIB-1014P has been initialized | Actions: - Assert GPIB IFC - Wait at least 100 microseconds - Unassert IFC...
  • Page 124 - Set or clear GPIB Remote Enable signal | Assumptions on entry: - User specified sre is non-zero if REN is to be asserted and is zero if REN is to be unasserted - GPIB-1014P is System Controller and Active Controller | Actions: - Check sre flag.
  • Page 125 | * RECEIVE - RCV* | * * * * * * * * * * * * * * * | Summary: - Called by READ to receive data if GPIB-1014P is Controller-In-Charge - Called directly from main program to receive data if...
  • Page 126 | Save d2 movb #FH,AUXMR.L | Release any handshake holdoff in progress b cic.L | Is GPIB-1014P Controller-In-Charge? RCV1 movb #AUXRA+0202,AUXMR.L | Yes--Set HLDE and BIN in AUXRA RCV2 RCV1: movb #AUXRA,AUXMR.L | No--Clear any HLDE or HLDA in effect...
  • Page 127 | Summary: - Called to read device-dependent (data) messages when the GPIB-1014P is Controller-In-Charge (RCV is called when the GPIB-1014P is Idle Controller) | Assumptions on entry: - GPIB-1014P is Controller-In-Charge - The Talker address is placed in first location of...
  • Page 128 #UNL,cmdbuf.L+1 addw #2,cmdct.L | Command routine will address the Talker movb #LTN,AUXMR.L | Program GPIB-1014P to be a Listener movb #GTS,AUXMR.L | so it can take control synchronously | later; then go to standby and drop ATN movw #datct,d0...
  • Page 129 | - The GPIB-1014P is Standby or Idle Controller | - GPIB-1014P is or will be addressed to talk | - If the GPIB-1014P is Idle Controller, the current CIC will go to standby - The d0 register contains the byte count...
  • Page 130 #DMAO,IMR2 | Enable DMA to the CDOR DSEND3: movl #-1,d0 | Return (-1) indicating error DSEND4: movl a6@(-8),d2 | Restore d2 movl a6@(-4),d1 | Restore d1 unlk | Unlink | Return GPIB-1014P User Manual C-14 © National Instruments Corporation...
  • Page 131 | Actions: - Set up cmdbuf and cmdct and call CMD to address the GPIB-1014P as Talker, to address the Listener, and to unaddress all other devices - Go to standby and unassert ATN - Transfer the contents of datct to the d0 register...
  • Page 132 | Source Handshake-Data will write data WRITE1: btst #DO,ISR1.L | Wait until last byte has been sent WRITE1 movb #TCA,AUXMR.L | Then take control subw #2,cmdct.L | Prepare to unaddress all Talkers and Listeners GPIB-1014P User Manual C-16 © National Instruments Corporation...
  • Page 133 | Summary: - Called by CMD to send interface command messages | Assumptions on entry: - The GPIB-1014P is Active Controller - The d0 register contains the number of bytes to send - The a0 register contains the address oc cmdbuf...
  • Page 134 | Summary: - Send GPIB interface or command messages | Assumptions on entry: - The GPIB-1014P is Controller-In-Charge - The commands to be sent are in cmdbuf - The variable cmdct contains the number of commands to be sent, which must be less than 256...
  • Page 135 - The primary GPIB address of the new controller is placed in tctadr | Actions: - Send TCA command to take control in case the GPIB-1014P is at standby - Set up the command buffer and command count - Call CMD to send the command bytes...

  • Page 136: Multiline Interface Command Messages

    Appendix D Multiline Interface Messages The following tables are multiline interface messages (sent and received with ATN TRUE). © National Instruments Corporation GPIB-1014P User Manual...
  • Page 137 Message Definitions Device Clear Parallel Poll Unconfigure Group Execute Trigger Selected Device Clear Go To Local Serial Poll Disable Local Lockout Serial Poll Enable My Listen Address Take Control Parallel Poll Configure Unlisten GPIB-1014P User Manual © National Instruments Corporation...
  • Page 138 MSA23,PPD MTA24 MSA24,PPD MTA25 MSA25,PPD MTA26 MSA26,PPD MTA27 MSA27,PPD MTA28 MSA28,PPD MTA29 MSA29,PPD MTA30 MSA30,PPD Message Definitions Parallel Poll Disable My Talk Address Parllel Poll Enable Serial Poll Enable My Secondary Address Untalk © National Instruments Corporation GPIB-1014P User Manual...

  • Page 139: Appendix E Operation Of The Gpib

    (Talker) to the receiver (Listener). The Controller addresses a Talker and a Listener before the Talker can send its message to the Listener. After the message is transmitted, the Controller may unaddress both devices. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 140: The Controller-In-Charge And System Controller

    NRFD (not ready for data) NRFD indicates when a device is ready or not ready to receive a message byte. The line is driven by all devices when receiving commands and by Listeners when receiving data messages. GPIB-1014P User Manual © National Instruments Corporation...

  • Page 141: Ndac (Not Data Accepted

    See Figures E-1, E-2, and E-3. The standard connector is the Amphenol or Cinch Series 57 Microribbon or Amp Champ type. An adapter cable using a non-standard cable and/or connector is used for special interconnection applications. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 142: Figure E-1. Gpib Connector And The Signal Assignment

    NRFD GND (TW PAIR W/NRFD) NDAC GND (TW PAIR W/NDAC) GND (TW PAIR W/IFC) GND (TW PAIR W/SRQ) GND (TW PAIR W/ATN) SHIELD SIGNAL GROUND Figure E-1. GPIB Connector and the Signal Assignment GPIB-1014P User Manual © National Instruments Corporation...

  • Page 143: Figure E-2. Linear Configuration

    Appendix E Multiline Interface Messages Figure E-2. Linear Configuration © National Instruments Corporation GPIB-1014P User Manual...

  • Page 144: Configuration Requirements

    A maximum separation of four meters between any two devices and an average separation of two meters over the entire bus. • A maximum total cable length of 20 m. • No more than 15 devices connected to each bus, with at least two-thirds powered on. GPIB-1014P User Manual © National Instruments Corporation...

  • Page 145: Related Document

    Related Document For more information on topics covered in this section, consult IEEE Standard Digital Interface for Programmable Instrumentation, IEEE-488 Std. 488-1978, IEEE-488.1 Std. 488-1987, and IEEE- 488.2 Std. 488-1987. © National Instruments Corporation GPIB-1014P User Manual...

  • Page 146: Appendix F Mnemonics Key

    VMEbus operations and signals. The mnemonic types in the key that follows are abbreviated to mean the following: Function Integrated Circuit Local Message Local Signal Register Remote Message System Function State VMEbus Operation VMEbus Signal © National Instruments Corporation GPIB-1014P User Manual...
  • Page 147 AUXRB Auxiliary Register B AUXRE Auxiliary Register E AWNS Acceptor Wait for New Cycle State BERR* Bus Error Binary Bit Block Transfer Controller CACS Controller Active State (C function) CADS Controller Addressed State GPIB-1014P User Manual © National Instruments Corporation...
  • Page 148 Data Accepted Holdoff on Device Trigger Active State Bit Data In Bit DI [7-0] Data In Bits 7 through 0 DI IE Enable Interrupt on Data In Bit Data In Register DIR[7-0] Data In Bits 7 through 0 © National Instruments Corporation GPIB-1014P User Manual...
  • Page 149 Group Execute Trigger Ground Go To Local Go to Standby HLDA Holdoff on All Bit HLDE Holdoff on End Bit IACK* Interrupt Acknowledge Signal IACKIN* Interrupt Acknowledge In IACKOUT* Interrupt Acknowledge Out IDTACK* Interrupt DTACK GPIB-1014P User Manual © National Instruments Corporation...
  • Page 150 Listener Primary Idle State Listen Local Unlisten LWLS Local With Lockout State LWORD* Low Word MCYC My Cycle MDTACK* DMA Acknowledge MJMN Major-Minor Bit My Listen Address My Secondary Address My Talk Address © National Instruments Corporation GPIB-1014P User Manual...
  • Page 151 Enable Interrupt on Remote Change Bit REMS Remote State Remote Enable REOS End on End Of String Received Bit Ready For Data Remote/Local Read-Modify-Write ROAK Release on Register Access Request Parallel Poll Request Service GPIB-1014P User Manual © National Instruments Corporation...
  • Page 152 Enable Interrupt on Service Request Input Bit SRQS Service Request State Status Byte STRS Source Transfer State SWNS Source Wait for New Cycle State SYSCLK* System Clock SYSFAIL* System Fail SYSRESET* System Reset © National Instruments Corporation GPIB-1014P User Manual...
  • Page 153 Talker Primary Idle State Three-State Timing Bit TRM[1-0] Transmit/Receive Mode Bits 1 through 0 Unconfigure Bit Unaligned Transfer Universal Command Group Unlisten command Untalk command Write XEOS Transmit End with End Of String Bit GPIB-1014P User Manual © National Instruments Corporation...

  • Page 154: Appendix G Customer Communication

    Spain (91) 640 0085 (91) 640 0533 Sweden 08-730 49 70 08-730 43 70 Switzerland 056/20 51 51 056/20 51 55 Taiwan 02 377 1200 02 737 4644 U.K. 0635 523545 0635 523154 © National Instruments Corporation GPIB-1014P User Manual...
  • Page 155 Technical Support Form ___________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
  • Page 156 GPIB-1014P Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Update this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
  • Page 157 • Type of other boards installed and their respective hardware settings: Base I/O Interrupt Board Type Address Level Channel...

  • Page 158: Austin, Tx

    Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: GPIB-1014P User Manual Edition Date: June 1994 Part Number: 370944A-01 Please comment on the completeness, clarity, and organization of the manual.

  • Page 159: Index

    (table), 4-28 to 4-34 overview, 4-27 to 4-28 Auxiliary Register 0 (ADR0), 4-43 Auxiliary Register A (AUXRA), 4-38 to 4-39 Auxiliary Register B (AUXRB), 4-40 to 4-41 Auxiliary Register E (AUXRE), 4-42 © National Instruments Corporation Index-1 GPIB-1014P User Manual...
  • Page 160 BIN (Binary Bit), 4-38 bus signals. See VMEbus. cable shield grounding, GPIB, 3-8 cabling, 3-10 to 3-11 capability codes for GPIB-1014P, 2-10 to 2-12 CDO[7-0] (Command/Data Out Bits 7 through 0), 4-7 CDOR. See Command/Data Out Register (CDOR). Chip Reset command...
  • Page 161 DMAO (DMA Out Enable Bit), 4-16 DO (Data Out Bit), 4-12 DO IE (Data Out Interrupt Enable Bit), 4-12 documentation for GPIB-1014P, E-7, vi don't care bits, definition, 4-2 DT (Disable Talker Bit), 4-44 DT0 (Disable Talker 0 Bit), 4-43 DT1 (Disable Talker 1 Bit), 4-45 ©...
  • Page 162 ERR (Error Bit), 4-11 to 4-12 ERR IE (Error Interrupt Enable Bit), 4-11 to 4-12 Execute Parallel Poll command codes for, 4-29 description, 4-34 features of GPIB-1014P, 1-1 Finish Handshake (FH) command codes for, 4-28 description, 4-31 GET (Group Execute Trigger) command, 4-25...
  • Page 163 IFC (interface clear) line, E-3 Immediate Execute Pon command codes for, 4-28 description, 4-30 IMR1. See Interrupt Mask Register 1 (IMR1). initialization of GPIB-1014P, 5-1 to 5-2 INITIALIZE-INIT sample program, C-5 to C-6 installation cabling, 3-10 to 3-11 hardware installation tests, 7-2 to 7-3...
  • Page 164 3-7 parts locator diagram, 3-2 for Supervisor or Non-privileged access, 3-3 VMEbus base address, 3-4 VMEbus interrupt configuration, 3-5 to 3-6 VMEbus interrupt line selection, 3-5 VMEbus interrupt priority code selection, 3-6 GPIB-1014P User Manual Index-6 © National Instruments Corporation...
  • Page 165 NDAC (not data accepted) signal, E-2 Non-Valid Secondary Command or Address command codes for, 4-28 description, 4-32 NRFD (not ready for data) signal, E-2 operating environment, A-1 optional equipment for GPIB-1014P, 1-3 © National Instruments Corporation Index-7 GPIB-1014P User Manual...
  • Page 166 READ, C-11 to C-12 RECEIVE-RCV, C-9 to C-10 REMOTE ENABLE-REN, C-8 WRITE, C-15 to C-16 sending/receiving messages, 5-7 serial polls, 5-8 Talker and Listener addressed implementation, 5-5 to 5-7 overview, 5-5 programmed implementation, 5-5 GPIB-1014P User Manual Index-8 © National Instruments Corporation...
  • Page 167 (Request Service Bit), 4-19 S8 (Serial Poll Status Byte), 4-19 S (Status Bit Polarity Bit), 4-37 sample programs 68000 code, C-2 to C-4 COMMAND SEND-CSEND, C-17 DATA SEND-DSEND, C-13 to C-14 INITIALIZE-INIT, C-5 to C-6 © National Instruments Corporation Index-9 GPIB-1014P User Manual...
  • Page 168 SH (Source Handshake), 4-7 signals and lines data lines, E-2 GPIB connector and signal assignment (illustration), E-4 GPIB-1014P pin assignment on VMEbus connector P1, 3-9 to 3-10 handshake lines, E-2 DAV (data valid), E-3 NDAC (not data accepted), E-2 NRFD (not ready for data), E-2...
  • Page 169 2-4 operation of, E-1 to E-2 overview, 5-5 programmed implementation, 5-5 sending/receiving messages, 5-7 VMEbus slave-addressing, 2-2 TCT (Take Control) command, 4-26 test and troubleshooting. See troubleshooting test procedures. © National Instruments Corporation Index-11 GPIB-1014P User Manual...
  • Page 170 7-2 to 7-3 interpreting test procedures, 7-1 overview, 6-5, 7-1 verification of GPIB-1014P before installation, 3-10 U (Parallel Poll Unconfigure Bit), 4-36 UNL (Unlisten) command, 4-26 unpacking the GPIB-1014P, 1-3 to 1-4 UNT (Untalk) command, 4-26...
  • Page 171 Index signals (chart), 2-1 to 2-2 slave-addressing, 2-2 to 2-3 slave-data, 2-3 WRITE sample program, C-15 to C-16 X (Don't Care Bit), 4-43 XEOS (Transmit END with EOS Bit), 4-38 © National Instruments Corporation Index-13 GPIB-1014P User Manual...

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