National Instruments Corporation GPIB-1014P User Manual page 163

H
handshake lines, E-2
hidden registers
Address Register 0 (ADR), 4-44
Address Register 1 (ADR1), 4-45
Auxiliary Register 0 (ADR0), 4-43
Auxiliary Register A (AUXRA), 4-38 to 4-39
Auxiliary Register B (AUXRB), 4-40 to 4-41
Auxiliary Register E (AUXRE), 4-42
End of String Register (EOSR), 4-46
Internal Counter Register (ICR), 4-35
Parallel Poll Register (PPR), 4-36 to 4-37
HLDA (Holdoff on All Bit), 4-39
HLDE (Holdoff on END Bit), 4-39
I
ICR. See Internal Counter Register (ICR).
IEEE-488 standard, 1-1
GPIB-1014P capabilities, 2-10 to 2-12
IEEE-1014 standard, 1-1
GPIB-1014P compliance levels, 2-12
IFC (interface clear) line, E-3
Immediate Execute Pon command
codes for, 4-28
description, 4-30
IMR1. See Interrupt Mask Register 1 (IMR1).
initialization of GPIB-1014P, 5-1 to 5-2
INITIALIZE-INIT sample program, C-5 to C-6
installation
cabling, 3-10 to 3-11
hardware installation tests, 7-2 to 7-3
prerequisites for, 3-1
unpacking the GPIB-1014P, 1-3 to 1-4
verification of system compatibility, 3-9
verification testing, 3-10
INT (Interrupt Bit), 4-14 to 4-15
INTERFACE CLEAR-IFC sample program, C-7
interface registers
Address Mode Register (ADMR), 4-22 to 4-24
Address Status Register (ADSR), 4-20 to 4-21
Auxiliary Mode Register (AUXMR), 4-27 to 4-34
Command/Data Out Register (CDOR), 4-7
Command Pass Through Register (CPTR), 4-25 to 4-26
Data In Register (DIR), 4-6
hidden registers
Address Register 0 (ADR), 4-44
Address Register 1 (ADR1), 4-45
Auxiliary Register 0 (ADR0), 4-43
© National Instruments Corporation Index-5
Index
GPIB-1014P User Manual