Auxiliary Register B (Auxrb) - National Instruments Corporation GPIB-1014P User Manual

Section Four

Auxiliary Register B (AUXRB)

VMEbus Address:
AUXMR Control Code: 101 (Binary, Bits 7 - 5)
Attributes:
4 3
INV
ISS
Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into the
Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the
AUXMR causes the Command Code to be written to AUXRB. When the data is written to
AUXRB, the bits are denoted as shown in the register bit map above. This 5-bit code affects
several interface functions, as described in the following paragraphs.
Bit Mnemonic
4w ISS
3w INV
2w TRI
© National Instruments Corporation
Base Address + B (hex)
Write Only,
Accessed through AUXMR
2 1
TRI SPEOI
Description
Individual Status Select Bit
The ISS bit determines the value of the TLC ist message. When ISS=1,
ist becomes the same value as the TLC Service Request State (SRQS).
(The TLC is asserting the GPIB SRQ message when it is in SRQS.)
When ISS=0, ist takes on the value of the TLC Parallel Poll Flag. The
Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and
Clear Parallel Poll Flag auxiliary commands.
Invert Bit
The INV bit affects the polarity of the TLC INT pin. Setting INV causes
the polarity of the Interrupt (INT) pin on the TLC to be active low. As
implemented on the GPIB-1014P, configuring the INT pin to active low
results in interrupt request errors. Consequently, INV should always be
clear and should never be set.
INV = 0 : INT pin is active high
INV = 1 : INT pin is active low
Three-State Timing Bit
The TRI bit determines the TLC GPIB Source Handshake Timing, T1, as
defined in the IEEE-488 specifications. TRI can be set to enable high-
speed data transfers when three-state GPIB drivers are used. (The GPIB-
1014P uses three-state GPIB drivers except during Parallel Poll
responses, in which case the GPIB drivers automatically switch to Open
4-41
0
CPT
ENABLE
W
Register Descriptions
GPIB-1014P User Manual