National Instruments Corporation GPIB-1014P User Manual page 170

Index
theory of operation
address decoding, 6-2
clock and reset circuitry, 6-2
GPIB interface, 6-4 to 6-5
interrupter logic, 6-3 to 6-4
test and troubleshooting, 6-5
timing control logic, 6-3
VMEbus interface, 6-1 to 6-2
timing control logic, 6-3
timing state machine, definition, 2-9
TLC. See Talker/Listener/Controller (TLC).
ton (Talk Only Bit), 4-22
TPAS (Talker Primary Addressed State Bit), 4-21
transceivers for GPIB-1014P, 2-2
TRI (Three-State Timing Bit), 4-40 to 4-41
Trigger command
codes for, 4-28
description, 4-31
TRM[1-0] (Transmit/Receive Mode Bits 1 through 0), 4-22 to 4-23
troubleshooting test procedures
hardware installation tests, 7-2 to 7-3
interpreting test procedures, 7-1
overview, 6-5, 7-1
verification of GPIB-1014P before installation, 3-10
U
U (Parallel Poll Unconfigure Bit), 4-36
UNL (Unlisten) command, 4-26
unpacking the GPIB-1014P, 1-3 to 1-4
UNT (Untalk) command, 4-26
V
Valid Secondary Command or Address command
codes for, 4-28
description, 4-32
verification
of system compatibility, 3-9
testing, 3-10
VMEbus
base address configuration, 3-3 to 3-4
control signals, 6-1 to 6-2
data lines, 6-1
definition, 2-9
interrupt configuration, 3-5 to 3-6
modules not provided, 2-5
GPIB-1014P User Manual Index-12 © National Instruments Corporation