Clock Generation - Xilinx SP701 User Manual

Clock Generation

The SP701 board provides an I2C programmable (10 MHz – 810 MHz) Si570 oscillator (U45) to
source the 200 MHz default SYSCLK. The U45 (I2C address 0x5D) I2C02_SYSOSC bus is
connected to U23 TCA9548A main I2C0 bus switch channel 1. The U45 Si570 LVDS output is
connected to FPGA U1 bank 33 MRCC pins AE8 (P) and AE7 (N). See the
section for U45 programming setup information.
The following table lists the clock types on the SP701 board.
Table 8: SP701 Clocks
Clock
SYS_CLK
DDR3L CK
ETH1/2_GTX_CLK
ETH1/2_RX_CLK
MIPI_CSI_CLK
MIPI_DSI_CLK
FMC_CLK0_M2C
FMC_CLK1_M2C
FMC_LA00_CC
FMC_LA01_CC
6x of PMOD_CLK
HDMI_CLK
The detailed FPGA connections for the clocks described in the table above are documented in
the SP701 board XDC file, referenced in
information, see the data sheet at the
The following figure shows the SP701 board clocking diagram.
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Direction Frequency
In to FPGA from Si570 33.3333 MHz
Out from FPGA to 400 MHz - 800 MHz
DDR3L
Out from FPGA to 125 MHz
DP83867IR
In to FPGA from 125 MHz
DP83867IR
In to FPGA from PCAM 672 MHz
Out from FPGA to LCD TBD
FMC LPC to FPGA Variable
FMC LPC to FPGA Variable
Out/In by FPGA for Variable
FMC LPC
Out/In by FPGA for Variable
FMC LPC
Out from FPGA to 6x Variable
PMOD connectors
Out from FPGA to 25 MHz - 165 MHz
ADV7511
Appendix B: Xilinx Design
Silicon Laboratories, Inc.
Chapter 3: Board Component Descriptions
I2C Bus Topology
I/O Standard
LVDS Bank 33, MRCC
DIFF_SSTL15 Bank 34, DQS
LVCMOS_33 Bank 33, SE I/O
LVCMOS_25 Bank 33, SRCC/MRCC
LVDS_25 Bank 33, SRCC/MRCC
HSTL_18 Bank 13, Diff I/O
LVDS_25/HSTL_18 Bank 36, MRCC
LVDS_25/HSTL_18 Bank 35, MRCC
LVDS_25/HSTL_18 Bank 36, SRCC
LVDS_25/HSTL_18 Bank 35, SRCC
LVCMOS_33 Bank 16, SE I/O
LVCMOS_33 Bank 15, SE I/O
Constraints. For more Si570
website.
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