Chapter 1: Introduction; Overview - Xilinx SP701 User Manual

Introduction

Overview

The SP701 evaluation board is based on the XC7S100FGGA676 device, a member of the Xilinx
7 series FPGA family. It is optimized for low cost, low power, and high I/O performance. It comes
with advanced high-performance FPGA logic based on real6-input look up table (LUT), 36 Kb
dual-port block RAM, support for DDR3L interface up to 1866 Mb/s, XADC with 12-bit
1 MSPA ADC with on-chip thermal and supply sensors, and powerful clock management tiles
(CMTs). The board is designed for high-performance and lower power with a 28 nm, 1V core
voltage process. For lower power, it has a 0.9V core voltage option.
Table 1: XC7S100 Resources
Spartan ® -7 FPGA
Resources
Logic Resources
Memory Resources
Clock Resources
I/O Resources
Embedded Hard IP
Resources
Speed Grades
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Component
Part Number
Logic Cells
Slices
CLB Flip-flops
Max. Distributed RAM (Kb)
Block RAM/FIFO w/EEC (36 Kb each)
Total Block RAM (Kb)
Clock Mgmt. Tiles (1 MMCM + 1 PLL)
Max. Single-Ended I/O Pins
Max. Differential I/O Pins
DSP Slices
Analog Mixed Signal (AMS)/XADC
Configuration AES/HMAC Blocks
Commercial Temp (C)
Industrial Temp (I)
Expanded Temp (Q)
Package Body Area (mm)
FGGA676 27 x 27

Chapter 1: Introduction

Chapter 1
XCS7100
102,400
16,000
128,000
1,100
120
4,320
8
400
192
160
1
1
-1, -2
-1, -2, -1L
-1
Ball Pitch (mm) Available User I/O:
3.3V SelectIO™
technology HR I/O
1.0 400
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